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Designing CODEC's to minimize DSP computational burden
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Opio, France, Apr. to be published
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R. Hester, "Designing CODEC's to minimize DSP computational burden," in Dig. Advanced Analog Circuit Design Workshop, Opio, France, Apr. 1999, to be published.
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Dig. Advanced Analog Circuit Design Workshop
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Hester, R.1
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A CMOS analog front-end circuit for an FDM-based ADSL system
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Dec.
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Chang, Z.1
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A BiCMOS analog front-end circuit for an FDM-based ADSL system
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Sept.
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D. Langford, B. Tesch, B. Williams, and G. Nelson, "A BiCMOS analog front-end circuit for an FDM-based ADSL system," IEEE J. Solid-State Circuits, vol. 33, pp. 1383-1393, Sept. 1998.
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Langford, D.1
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A 0.5 mm CMOS ADSL analog front-end IC
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Feb.
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Cornil, J.1
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A CMOS analog front-end IC for DMT ADSL
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Feb.
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C. Conroy, S. Sheng, A. Feldman, G. Uehara, A. Yeung, C.-J. Hung, V. Subramanian, P. Chiang, P. Lai, X. Si, J. Fan, D. Flynn, and M. He, "A CMOS analog front-end IC for DMT ADSL," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 240-241.
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Si, X.10
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7
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A 10-b 20 Msample/s analog-to-digital converter
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Mar.
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S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T. Viswanathan, "A 10-b 20 Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
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A low-power 12b analog-to-digital converter with on-chip precision trimming
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Apr.
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M. de Wit, K.-S. Tan, and R. Hester, "A low-power 12b analog-to-digital converter with on-chip precision trimming," IEEE J. Solid-State Circuits, vol. 28, pp. 455-461, Apr. 1993.
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De Wit, M.1
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9
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0024898312
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A self-calibrated technique for monolithic high-resolution D/A converters
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Dec.
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D. Groeneveld, H. Schouwenaars, H. Termeer, and C. Bastiaansen, "A self-calibrated technique for monolithic high-resolution D/A converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
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