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Volumn 31, Issue 9, 1996, Pages 268-278

Improving cache performance with balanced tag and data paths

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EID: 17044435121     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/248209.237202     Document Type: Article
Times cited : (2)

References (25)
  • 1
    • 0027192667 scopus 로고
    • Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
    • May
    • A. Agarwal, and S. Pudar, "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches," Proc. of 20th Int'l Symp. on Computer Architecture, May 1993, pp. 179-190.
    • (1993) Proc. of 20th Int'l Symp. on Computer Architecture , pp. 179-190
    • Agarwal, A.1    Pudar, S.2
  • 3
    • 2842568131 scopus 로고
    • Internal Architecture of Alpha 21164 Microprocessor
    • Mar.
    • P. Bannon, and J. Keller, "Internal Architecture of Alpha 21164 Microprocessor," Proc. COMPCON'95, Mar. 95, pp. 79-87.
    • (1995) Proc. COMPCON'95 , pp. 79-87
    • Bannon, P.1    Keller, J.2
  • 4
    • 0026257568 scopus 로고
    • A 2ns Cycle, 3.8ns Access 512KB CMOS ECL RAM with a Fully Pipelined Architecture
    • Nov.
    • T. Chappell, et.al., "A 2ns Cycle, 3.8ns Access 512KB CMOS ECL RAM with a Fully Pipelined Architecture," IEEE Journal of Solid-State Circuits, Vol. 26(11), Nov. 1991, pp. 1577-1585.
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , Issue.11 , pp. 1577-1585
    • Chappell, T.1
  • 5
    • 0027640963 scopus 로고
    • Cache Performance of the SPEC92 Benchmark Suite
    • Aug.
    • J. Gee, M. Hill, D. Pnevmatikatos, and A. Smith, "Cache Performance of the SPEC92 Benchmark Suite," IEEE Micro, Vol. 13(4), Aug. 1993, pp. 17-27.
    • (1993) IEEE Micro , vol.13 , Issue.4 , pp. 17-27
    • Gee, J.1    Hill, M.2    Pnevmatikatos, D.3    Smith, A.4
  • 7
    • 85063333625 scopus 로고
    • UltraSPARC: The Next Generation Superscalar 64-bit SPARC
    • Mar.
    • D. Greenley et al., "UltraSPARC: The Next Generation Superscalar 64-bit SPARC," Proc. COMPCON'95, Mar. 95, pp. 442-451.
    • (1995) Proc. COMPCON'95 , pp. 442-451
    • Greenley, D.1
  • 9
    • 0024173488 scopus 로고
    • A Case for Direct-Mapped Caches
    • Dec.
    • M. Hill "A Case for Direct-Mapped Caches," IEEE Computer, Vol. 21(12), Dec. 1988, pp. 25-40.
    • (1988) IEEE Computer , vol.21 , Issue.12 , pp. 25-40
    • Hill, M.1
  • 10
    • 0003984121 scopus 로고
    • Meta-Software Inc
    • HSPICE User's Manual, Meta-Software Inc, 1992.
    • (1992) HSPICE User's Manual
  • 11
    • 0027658596 scopus 로고
    • Designing High Performance Processors Using Real-Address Prediction
    • Sep.
    • K. Hua, L. Liu, and J.-K. Peir, "Designing High Performance Processors Using Real-Address Prediction," IEEE Transactions on Computers, C-42(9), Sep. 1993, pp. 1146-1151.
    • (1993) IEEE Transactions on Computers , vol.C-42 , Issue.9 , pp. 1146-1151
    • Hua, K.1    Liu, L.2    Peir, J.-K.3
  • 12
    • 85023980169 scopus 로고
    • Advanced Performance Features of the 64-bit PA-8000
    • Mar.
    • D. Hunt, "Advanced Performance Features of the 64-bit PA-8000," Proc. COMPCON'95, Mar. 95, pp. 123-128.
    • (1995) Proc. COMPCON'95 , pp. 123-128
    • Hunt, D.1
  • 14
    • 3342935940 scopus 로고
    • The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor
    • Mar.
    • D. Levitan, T. Thomas, and P. Tu, "The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor," Proc. COMPCON'95, Mar. 1995, pp. 285-291.
    • (1995) Proc. COMPCON'95 , pp. 285-291
    • Levitan, D.1    Thomas, T.2    Tu, P.3
  • 15
    • 2842582480 scopus 로고
    • Product Overview, Oct.
    • MIPS Technologies Inc. "R10000 Microprocessor," Product Overview, Oct. 1994.
    • (1994) R10000 Microprocessor
  • 16
    • 0026103250 scopus 로고
    • An Area Model for On-Chip Memories and its Application
    • Feb.
    • J. Mulder, N. Quach, and M. Flynn, "An Area Model for On-Chip Memories and its Application," IEEE Journal of Solid-State Circuits, Feb. 1991, Vol. 26(2), pp. 98-106.
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , Issue.2 , pp. 98-106
    • Mulder, J.1    Quach, N.2    Flynn, M.3
  • 20
    • 0020177251 scopus 로고
    • Cache Memories
    • Sep.
    • A. Smith, "Cache Memories," Computing Surveys, 14(4), Sep. 1982, pp. 473-530.
    • (1982) Computing Surveys , vol.14 , Issue.4 , pp. 473-530
    • Smith, A.1
  • 21
    • 0024034266 scopus 로고
    • Cache Operations by MRU Change
    • Jun.
    • K. So, and R. Rechtschaffen, "Cache Operations by MRU Change," IEEE Trans. on Computers, C-37(6), Jun. 1988, pp. 700-709.
    • (1988) IEEE Trans. on Computers , vol.C-37 , Issue.6 , pp. 700-709
    • So, K.1    Rechtschaffen, R.2
  • 22
    • 0041163288 scopus 로고
    • System Performance Evaluation Cooperative, SPEC News-letter, 1990.
    • (1990) SPEC News-letter
  • 24
    • 0026904396 scopus 로고
    • An Analytical Access Time Model for On-Chip Cache Memories
    • Aug.
    • T. Wada, S. Rajan, and S. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories," IEEE Journal of Solid-State Circuits, Vol. 27(8), Aug. 1992, pp. 1147-1156.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.8 , pp. 1147-1156
    • Wada, T.1    Rajan, S.2    Przybylski, S.3
  • 25
    • 0003650381 scopus 로고
    • An Enhanced Access and Cycle Time Model for On-Chip Caches
    • Jul.
    • S. Wilton, and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," DEC WRL Research Report 93/5, Jul. 1994.
    • (1994) DEC WRL Research Report 93/5
    • Wilton, S.1    Jouppi, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.