Fast, accurate prediction of PLL jitter induced by power grid noise

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 121-124

  Lai, Xiaolue ^a   Roychowdhury, Jaijeet ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICRON (DCM); GRID NOISE; MACROMODELS; PHASE ERRORS;

COMPUTER SIMULATION; ELECTRIC POTENTIAL; PERTURBATION TECHNIQUES; PHASE LOCKED LOOPS; POWER SUPPLY CIRCUITS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

JITTER;

EID: 17044431348     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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