Low leakage circuit design for FPGAs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 715-718

  Ciccarelli, Luca ^a   Lodi, Andrea ^a   Canegallo, Roberta ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; LEAKAGE CURRENTS; NETWORK PROTOCOLS; SIGNAL PROCESSING; SOFTWARE ENGINEERING; THRESHOLD VOLTAGE; TRANSISTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

CIRCUIT DESIGN; INTEGRATED TRANSISTORS; LOW THRESHOLD TRANSISTORS; SIGNAL TRANSMISSION DELAY;

SWITCHING CIRCUITS;

EID: 17044424987     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Jason H. Andersen, Fand N. Najm, and Tim Tuan Active Leakage Power Optimization for FPGA In FPGA2004, February 22-24, 2004
2. A. Rahman, V. Polavarapuv Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays In FPGA2004, February 22-24, 2004
3. Liqiong Wei, Zhanping Chen et al. Design and Optimization of Low Voltage High Performance Dual Threshold In DAC1998, 1998
4. A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo and R. Guerrieri. A Pipelined Configurable Gate Array for Embedded Processors In Proceedings of the 11th ACM/SIGDA International Symposium on FPGAs, February 2003.
5. G. Lemieux and D. Lewis. Circuit Design of Routing Switches In ACM/SIGDA International Symposium on FPGAs, February, 2002
6. Michael Powell, Se-Hyun Yang et al. Gated-Vdd: A circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories5 In ISPLED 2000, 2000