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Volumn , Issue , 2004, Pages 435-438

Sequential synthesizable embedded programmable logic cores for system-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CIRCUITS; OPTIMIZATION; TABLE LOOKUP;

EID: 17044398933     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (14)
  • 7
    • 0037344580 scopus 로고    scopus 로고
    • A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customisable I/O"
    • March
    • M. Borgatti, F. Lertora, B. Foret, L. Cali, "A Reconfigurable System featuring Dynamically Extensible Embedded Microprocessor, FPGA, and Customisable I/O", IEEE Journal of Solid-State Circuits, vol. 38, no. 3, March 2003, pp. 521-529.
    • (2003) IEEE Journal of Solid-State Circuits , vol.38 , Issue.3 , pp. 521-529
    • Borgatti, M.1    Lertora, F.2    Foret, B.3    Cali, L.4
  • 12
    • 33746950420 scopus 로고    scopus 로고
    • Combinational logic synthesis for LUT based field programmable gate array
    • April
    • J. Cong and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Array", ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 2, pp. 145-204, April 1996.
    • (1996) ACM Trans. Design Automation of Electronic Systems , vol.1 , Issue.2 , pp. 145-204
    • Cong, J.1    Ding, Y.2
  • 13
    • 0011840160 scopus 로고    scopus 로고
    • A packet switching communication-based test access mechanism for system chips
    • Mohsen Nahvi, Andre Ivanov, "A Packet Switching Communication-Based Test Access Mechanism for System Chips", in Proceedings of the IEEE European Test Workshop, 2001, pp. 81-86.
    • (2001) Proceedings of the IEEE European Test Workshop , pp. 81-86
    • Nahvi, M.1    Ivanov, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.