νMOS-based sorter for arithmetic applications

VLSI Design

Volumn 11, Issue 2, 2000, Pages 129-136

  Rodriguez Villegas E ^a,b,c   Avedillo, M J ^a   Quintana, J M ^a,b   Huertas, G ^a   Rueda, A ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

^b UNIVERSITY OF SEVILLE   (Spain)

^c INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; THRESHOLD LOGIC;

ARITHMETIC CIRCUITS; SORTER CIRCUITS;

VLSI CIRCUITS;

EID: 1642633461     PISSN: 1065514X     EISSN: None     Source Type: None    
DOI: 10.1155/2000/57240     Document Type: Article

References (9)

1. Lamagna, E. A., "The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting and Merging", IEEE Trans. on Computers, C-28, 773-782, October, 1979.
2. Batcher, K. E. (1968). "Sorting Networks and their Applications", In: Proc. 1968 SICC, AFIPS, 32, 307-314.
3. Piestrak, S. J., "The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks", IEEE Trans. on Computers, 42, 700-712, June, 1993.
4. Shibata, T. and Ohmi, T. (1990). "A Functional MOS Transistor Featuring Gate Level Weighted Sum and Threshold Operations", IEEE Trans. on Electron Devices, 39(6), 1444-1455.
5. Rodriguez, E., Quintana, J. M., Avedillo, M. J. and Rueda, A., "Sorting Networks Implemented as vMOS Circuits", Electronics Letters, 34(23), 2237-2238, November, 1998.
6. Leblebici, Y., Özdemir, H., Kepkep, A. and Çilingiroglu, U., "A Compact (8 × 8)-Bit Serial/Parallel Multiplier Based on Capacitive Threshold Logic", Proc. of the ECCTD'95, pp. 55-58.
7. Özdemir, H., Kepkep, A., Pamir, B., Leblebici, Y. and Çilingiroglu, U., "A Capacitive Threshold-Logic Gate", IEEE Trans. on Solid-State Circuits, 31(8), 1141-1150, August, 1996.
8. Muroga, S., Threshold Logic and its Applications, John Wiley & Sons, 1971.
9. Song, P. J. and De Micheli, G., "Circuit and architecture trade-off for high-speed multiplication", IEEE Trans. on Solid-State Circuits, 26(9), 1184-1198, September, 1991.