Device architecture and reliability aspects of a novel 1.22 μm 2 EEPROM cell in 0.18 μm node for embedded applications

Microelectronic Engineering

Volumn 72, Issue 1-4, 2004, Pages 415-420

  Tao, G ^a   Scarpa, A ^a   Van Dijk, K ^a   Van Marwijk, L ^a   Dormans, D ^a   Garbe, J ^b   Boter, D ^a   Verhaar, R ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

Build in reliability; Data retention; EEPROM; NVM; SILC

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC POTENTIAL; ELECTRON TUNNELING; EMBEDDED SYSTEMS; GATES (TRANSISTOR); LEAKAGE CURRENTS; TRANSMISSION ELECTRON MICROSCOPY;

BUILD-IN RELIABILITY; DATA RETENTION; NVM; SILC;

PROM;

EID: 1642618673     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.01.024     Document Type: Conference Paper

References (5)

1. Bill C.S., et al. IEEE J. Solid-State Circuits. SC-20(5):1985;979-985.
2. D. Dormans et al., in NVSMW 2003.
3. D. Dormans et al., SSDM 2001.
4. G. Tao et al., in: NVSMW 2001, pp. 103-131.
5. G. Tao et al., in: IRPS 2003 proceedings, pp. 604-605.