High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 2, 2004, Pages 218-226

  Yang, Meng Da ^a,b   Wu, An Yeu ^a,b   Lai, Jyh Ting ^a,b  

^a Graduate Institute of Electronics Engineering   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Adaptive decision feedback equalizer (ADFE); Predictive parallel branch slicer (PPBS) scheme; Relaxed look ahead ADFE

Indexed keywords

ADAPTIVE DECISION FEEDBACK EQUALIZER (ADFE); PREDICTIVE PARALLEL BRANCH SLICER (PPBS) SCHEME; RELAXED LOOK-AHEAD ADFE;

ALGORITHMS; COMPUTER SIMULATION; DECISION FEEDBACK EQUALIZERS; ELECTRIC FILTERS; ITERATIVE METHODS; LEAST SQUARES APPROXIMATIONS; PHASE SHIFT KEYING; PREDICTIVE CONTROL SYSTEMS; PULSE AMPLITUDE MODULATION; SIGNAL TO NOISE RATIO;

VLSI CIRCUITS;

EID: 1642352711     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.820521     Document Type: Conference Paper

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