The Advanced Encryption Standard on an Asynchronous Shared-memory Multiprocessor

Proceedings of the International Conference on VLSI

Volumn , Issue , 2003, Pages 379-381

  Smith, Scott F ^a  

^a Boise State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER HARDWARE; CRYPTOGRAPHY; ENCODING (SYMBOLS); INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; USER INTERFACES;

ASYNCHRONOUS BUS SYSTEM; SHARED MEMORY MULTIPROCESSORS;

INTERCONNECTION NETWORKS;

EID: 1642312141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. th Biennial University / Government / Industry Microelectronics Symposium, 2003.
2. Specification for the Advanced Encryption Standard, Federal Information Processing Standards Publication 197, National Institute of Standards and Technology, 2001.
3. S. Smith, "ARM 32-bit Implementation of the Advanced Encryption Standard," CoEn.BoiseState.edu/SSmith/AESCode.htm.
4. nd Edition, Addison-Wesley, 2000.
5. S. Smith, "VHDL Code for Asynchronous Bus Architecture Performance Evaluation," CoEn.BoiseState.edu/SSmith/AsynchBusVHDL/AsynchBus VHDL.htm.
6. S. Smith, "A Multiple-clock-domain Bus Architecture using Asynchronous FIFOs as Elastic Elements," Ph. D. Dissertation, University of Idaho, 2003.
7. www.ARM.com.
8. International Technology Roadmap for Semiconductors, public.itrs.net, 2001.
9. P. Kocker, J. Jaffe, and B. Jun, "Differential Power Analysis, " Advances in Cryptology: Proceedings of CRYPTO '99, Spring-Verlag, pp. 388-397, 1999.