Shared cache architectures for decision support systems

Performance Evaluation

Volumn 49, Issue 1-4, 2002, Pages 283-298

  Dubois, Michel ^a   Jeong, Jaeheon ^b   Nanda, Ashwini ^c  

^a University of Southern California ^*  (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Cache memory; Cold start bias; IO strategy; TPC H; Trace driven simulation

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DATABASE SYSTEMS; DYNAMIC RANDOM ACCESS STORAGE; MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; REAL TIME SYSTEMS; TELECOMMUNICATION TRAFFIC; WORLD WIDE WEB;

COLD START BIAS; IO STRATEGY; TPC-H; TRACE DRIVEN SIMULATION;

DECISION SUPPORT SYSTEMS;

EID: 1642272290     PISSN: 01665316     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0166-5316(02)00135-9     Document Type: Conference Paper

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