Modified reduced adder graph algorithm for multiplierless FIR filters

Electronics Letters

Volumn 41, Issue 6, 2005, Pages 302-303

  Xu, F ^a   Chang, C H ^a   Jong, C C ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMMON SUBEXPRESSION ELIMINATION (CSE) TECHNIQUES; MODIFIED REDUCED ADDER GRAPH (MRAG); N-DIMENSIONAL REDUCED ADDER GRAPH (RAG-N) ALGORITHMS; ODD FUNDAMENTAL (OF) GRAPHS;

ADDERS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; FORMAL LOGIC; GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL OPERATORS;

FIR FILTERS;

EID: 16244422685     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20057392     Document Type: Article

References (5)

1. Dempster, A.G., and Macleod, M.D.: 'Use of minimum-adder multiplier blocks in FIR digital filters', IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 1995, 42, (9), pp. 569-577
2. Paško, R., Schaumont, P., Derudder, V., Vernalde, S., and Ďuračková, D.: 'A new algorithm for elimination of common subexpressions', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1999, 18, (1), pp. 58-68
3. Peiró, M.M., Boemo, E.I., and Wanhammar, L.: 'Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm', IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., 2002, 49, (3), pp. 196-203
4. Xu, F., Chang, C.H., and Jong, C.C.: 'A new contention resolution algorithm for the design of minimal logic depth multiplierless filters'. Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004, III, pp. 481-484
5. Vinod, A.P., Lai, E.M., Premkuntar, A.B., and Lau, C.T.: 'FIR filter implementation by efficient sharing of horizontal and vertical common subexpressions', Electron. Lett., 2003, 39, (2), pp. 251-253