Complementary sidewall-spacer-diffused ultrashallow SD extension process for damascene independently-double-gated SOI CMOS

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 104-105

  Parke, S ^a,b   Goldston, M ^a   Hackler, D ^a   DeGregorio, K ^a   Hayhurst, R ^a   Horvath, A ^c   Parsa, S ^c  

^a AMERICAN SEMICONDUCTOR INC   (United States)

^b BOISE STATE UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH LAMP ANNEALING (FLA); PHOSPHOSILICATE GLASS (PDG); RING OSCILLATORS; SOURCE/DRAIN EXTENSIONS (SDE);

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; DIFFUSION; GLASS; ION IMPLANTATION; MOS DEVICES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PLASMA ETCHING; RAPID THERMAL ANNEALING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 16244419344     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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5. T. Ito, et. al., IEEE TSM, Vol. 16, pp. 417-422, Aug. 2003.
6. S.D. Kim, et. al., IEEE TED, Vol. 49, pp. 1748-1754, Oct. 2002