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Volumn , Issue , 1998, Pages 370-376

PSCP: A scalable parallel ASIP architecture for reactive systems

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGN APPROACH; INSTRUCTION SET; PROCESSING ELEMENTS; REACTIVE SYSTEM; REGISTER FILES; STATECHARTS; STATIC TIMING ANALYSIS; STEPPER MOTOR;

EID: 16244417998     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655884     Document Type: Conference Paper
Times cited : (5)

References (18)
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    • Drusinsky, D.1
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    • A state assignment procedure for single-block implementation of state-charts
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    • D. Drusinsky-Yoresh: A State Assignment Procedure for Single-Block Implementation of State-charts. IEEE Trans. on CAD, vol. 10, No 12, December 1991.
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    • Drusinsky-Yoresh, D.1
  • 7
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    • Gajski, D.1    Vahid, F.2    Gong, J.3
  • 9
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    • Instruction set matching and selection for dsp and asip code generation
    • Paris, France
    • C. Liem, T. May, P. Paulin: Instruction set matching and selection for DSP and ASIP code generation, Proc. of the EDAC-ETC-EUROASIC, Paris, France, 1994, p. 31-37.
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    • Liem, C.1    May, T.2    Paulin, P.3
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    • Computer organization and design
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    • The Hardware Software Interface
    • Patterson, D.A.1    Hennessy, J.L.2
  • 14
    • 0029184479 scopus 로고    scopus 로고
    • Timing constraint petri nets and their application to schedulability analysis of real-time system specifications
    • J. Tsai, S. Yang, Y.-H. Chang: Timing Constraint Petri Nets and Their Application to Schedulability Analysis of Real-Time System Specifications, IEEE Trans. Softw. Eng., vol. 21, no 1, pp. 32-49.
    • IEEE Trans. Softw. Eng. , vol.21 , Issue.1 , pp. 32-49
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.