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Volumn , Issue , 2004, Pages 280-285

Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps

Author keywords

Architectures; Receiver; Ultra Wideband

Indexed keywords

BANDWIDTH; BIT ERROR RATE; BROADBAND NETWORKS; DATA TRANSFER; PRODUCT DESIGN; PULSE MODULATION; RADIO COMMUNICATION; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 16244401642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013305     Document Type: Conference Paper
Times cited : (28)

References (16)
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    • Deschans, D.1
  • 4
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    • J. Vandenbussche et al. "Systematic design of a 200MS/s 8bit interpolating/averaging A/D converter". In Design Automation Conference, volume 39, pages 449-454, 2002.
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    • Vandenbussche, J.1
  • 6
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    • Digital architecture for an ultra-wideband radio receiver
    • October
    • R. Blazquez et al. "Digital Architecture for an Ultra-Wideband Radio Receiver". In VTC Fall '03, Orlando, FA, October 2003.
    • (2003) VTC Fall '03, Orlando, FA
    • Blazquez, R.1
  • 7
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    • 18 GHz low-power CMOS static frequency divider
    • October
    • Z. Gu and A. Thiede. "18 GHz low-power CMOS static frequency divider". Electronics Letters, 39:1433-1434, October 2003.
    • (2003) Electronics Letters , vol.39 , pp. 1433-1434
    • Gu, Z.1    Thiede, A.2
  • 10
    • 0031652007 scopus 로고    scopus 로고
    • A fully integrated 2.7V 0.35μm CMOS VCO for 5GHz wireless applications
    • February
    • P. Kinget. "A Fully Integrated 2.7V 0.35μm CMOS VCO for 5GHz Wireless applications". In International Solid-State Circuits Conference 1998, pages 226-227, February 1998.
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  • 12
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    • A channelized digital ultrawideband receiver
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    • W. Namgoong. "A Channelized Digital Ultrawideband Receiver". In IEEE Transactions on Wireless Communications, volume 2, pages 502-510, May 2003.
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.