SPIN-TEST: Automatic test pattern generation for speed-independent circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 903-908

  Shi, Feng ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); AYNCHRONOUS CIRCUITS; SPEED-INDEPENDENT CIRCUITS; SUBMICRON TECHNOLOGY;

ALGORITHMS; BENCHMARKING; DISCRETE FOURIER TRANSFORMS; FEEDBACK; GRAPH THEORY; MATHEMATICAL MODELS; OPTIMIZATION; PATTERN RECOGNITION; SYNCHRONIZATION;

NETWORKS (CIRCUITS);

EID: 16244379201     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382703     Document Type: Conference Paper

References (16)

1. C. Tristam, "It's time for clockless," Technology Review, pp. 37-41, 2001.
2. P. J. Hazewindus, "Testing delay insensitive circuits," Ph.D. Thesis, Department of Computer Science, California Institute of Technology, 1992.
3. H. Hulgaard, S. M. Burns, and G. Borriello, "Testing asynchronous circuits: A survey," Technical Report CS-TR-94-03-06, Department of Computer Science and Engineering, University of Washington, 1994.
4. M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin, "Partial-scan delay fault testing of asynchronous circuits," IEEE Transactions on Computers, vol. 17, pp. 1184-1198, 1998.
5. C. J. Myers, Asynchronous Circuit Design, John Wiley and Sons, Inc., New York, 2001.
6. S. Banerjee, S. T. Chakradhar, and R. K. Roy, "Synchronous test generation model for asynchronous circuits," in Proceedings of the 9th International Conference on VLSI Design, 1996, pp. 178-85.
7. O. Roig, J. Cortadella, M. A. Peiia, and E. Pastor, "Automatic generation of synchronous test patterns for asynchronous circuits," in Proceedings of the 34th Design Automation Conference, 1997, pp. 620-625.
8. K.-T. Cheng, V. D. Agrawal, and E. S. Kuh, "A simulation-based method for generating tests for sequential circuits," IEEE Transactions on Computers, vol. 39, no. 12, pp. 1456-1463, 1990.
9. F. Shi and Y. Makris, "Fault simulation and random test generation for speed-independent circuits," in Proceedings of the 2004 Great Lakes Symposium on VLSI, pp. 127-130, 2004.
10. Stuart Russell and Peter Norvig, Artificial Intelligence: A Modern Approach, Prentice Hall, New Jersey, 2002.
11. H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Transactions on Computers, vol. C-32, no. 12, pp. 1137-1144, 1983.
12. J. E. Chen, C. L. Lee, and W. J. Shen, "Single-fault fault-collapsing analysis in sequential logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 12, pp. 1559-1568, 1991.
13. H. K. Lee and D. S. Ha, On the Generation of Test Patterns for Combinational Circuits, Technical Report No. 12.93, Dep't of Electrical Eng., Virginia Polytechnic Institute, 1993.
14. F. Shi and Y. Makris, "Spin-sim: Logic and fault simulation for speed-independent circuits," in Proceedings of International Test Conference, 2004.
15. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, "Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Transactions on Information and Systems, vol. E80-D, no. 3, pp. 315-325, 1997.
16. Oriol Roig, "Personal communication," 2004.