Impact of Selective Process Bias (SPB) of interconnects on circuit delay

Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04

Volumn , Issue , 2004, Pages 155-158

  Kulkarni, Mak ^a   Nagaraj, N S ^a   Marshall, Andrew ^a   Le, Viet ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COMPUTER SIMULATION; DATABASE SYSTEMS; DELAY CIRCUITS; ELECTRIC RESISTANCE; INDUCTANCE; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC);

MOORE' LAW; OPTICAL PROXIMITY CORRECTION (OPC); RING OSCILLATOR STRUCTURES; SELECTIVE PROCESS BIAS (SPB); SEMICONDUCTOR TECHNOLOGY;

OPTICAL INTERCONNECTS;

EID: 16244379198     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dcas.2004.1360449     Document Type: Conference Paper

References (1)

1. ITRS 2003 Edition, http://public.itrs.net/Files/2003ITRS/ExecSum2003.pdf