Improved clock-gating through transparent pipelining

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 26-31

  Jacobson, Hans M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Adaptive pipeline depth; Circuits; Clock gating; Dynamic pipeline scaling; High performance; Low power; Microarchitecture; Optimal pipeline clocking; Pipeline stage unification; Transparent pipeline

Indexed keywords

CLOCKS; COMPUTER SIMULATION; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; TRANSISTORS; VLSI CIRCUITS;

ADAPTIVE PIPELINE DEPTH; CLOCK GATING; DYNAMIC PIPELINE SCALING; LOW POWER; MICROARCHITECTURE; OPTIMAL PIPELINE CLOCKING; PIPELINE STAGE UNIFICATION; TRANSPARENT PIPELINE;

INTEGRATED CIRCUIT LAYOUT;

EID: 16244364013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013248     Document Type: Conference Paper

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