Minimal adaptive routing on the mesh with bounded queue size

Journal of Parallel and Distributed Computing

Volumn 34, Issue 2, 1996, Pages 154-170

  Chinn, Donald D ^a,c   Leighton, Tom ^b   Tompa, Martin ^a  

^a University of Washington   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c YORK UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 16144366410     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1006/jpdc.1996.0052     Document Type: Article

References (28)

1. 1. Bar-Noy, A., Raghavan, P., Schieber, B., and Tamaki, H. Fast deflection routing for packets and worms. In Proceedings of the Twelfth Annual ACM Symposium on Principles of Distributed Computing, 1993, pp. 75-86.
2. 2. Batcher, K. E., Design of a massively parallel processor. IEEE Trans. Comput. 29, (Sept. 1980), 836-840.
3. 3. Ben-Aroya, I., Chinn, D. D., and Schuster, A. A lower bound for nearly minimal adaptive and hot potato algorithms. Submitted for publication.
4. 4. Ben-Aroya, I., and Schuster, A. A CLT-type lower bound for routing permutations on the mesh by short-sighted a-bounded hot-potato algorithms. Technical Report LPCR #9405, CS Department, Technion, 1994.
5. 5. Borodin, A., and Hopcroft, J. E. Routing, merging, and sorting on parallel models of computation. J. Computer and System Sciences, 30:130-145, 1985.
6. 6. Borodin, A., Raghavan, P., Schieber, B., and Upfal, E. How much can hardware help routing? Proceedings of the Twenty Fifth Annual ACM Symposium on Theory of Computing. 1993, pp. 573-582.
7. 7. Brassil, J. T. and Cruz, R. L. Bounds on maximum delay in networks with deflection routing. 29th Annual Allerton Conference on Communication, Control, and Computing. 1991, pp. 571-580.
8. 8. Chien, A., and Kim, J. H. Planar-adaptive routing: Low-cost adaptive networks for multiprocessors. Proceedings of the 19th International Symposium on Computer Architecture. 1992, pp. 268-277.
9. 9. Cypher, R., and Gravano, L. Adaptive, deadlock-free packet routing in torus networks with minimal storage. 1992 International Conference on Parallel Processing. 1992, pp. 204-211.
10. 10. Feige, U., and Raghavan, P. Exact analysis of hot-potato routing. Proceedings 33rd Annual Symposium on Foundations of Computer Science. Pittsburgh, PA, 1992, pp. 553-562.
11. 11. Hajek, B. Bounds for evacuation time for deflection routing. Distrib. Comput. 5 (1991), 1-6.
12. 12. Han, T., and Stanat, D. "Move and smooth" routing algorithms on mesh-connected computers. 28th Annual Allerton Conference on Communication, Control, and Computing. 1990, pp. 236-245.
13. 13. Intel. A Touchstone DELTA system description. Technical report, Intel, Portland, OR, 1991.
14. 14. Kaklamanis, C., Krizanc, D., and Rao, S. Hot-potato routing on processor arrays. Proceedings of the 1993 ACM Symposium on Parallel Algorithms and Architectures. 1993, pp. 273-272.
15. 15. Kaklamanis, C., Krizanc, D., and Tsantilas, T. Tight bounds for oblivious routing in the hypercube. Proceedings of the 1990 ACM Symposium on Parallel Algorithms and Architectures. 1990, pp. 31-36.
16. 16. Krizanc, D. Oblivious routing with limited buffer capacity. J. Comput. System Sci. 43 (1991), 317-327.
17. 17. Kunde, M. Routing and sorting on mesh-connected arrays. 3rd Aegean Workshop on Computing (AWOC), Lecture Notes in Computer Science, Vol. 319. Springer-Verlag, Berlin/New York, 1988, pp. 423-433.
18. 18. Leighton, F. Thomson Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann, San Mateo CA, 1992.
19. 19. Leighton, T. Average case analysis of greedy routing algorithms on arrays. Proceedings of the 1990 ACM Symposium on Parallel Algorithms and Architectures. 1990, pp. 2-10.
20. 20. Leighton, T., Makedon, F., and Tollis, I. A 2n - 2 step algorithm for routing in an n × n array with constant size queues. Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures. 1989, pp. 328-335.
21. 21. Lenoski, D., Laudon, J., Joe, T., Nakahira, D., Stevens, L., Gupta, A., and Hennessy, J. The DASH prototype: Implementation and performance. Proc. 19th Annual Symposium on Computer Architecture. 1992, pp. 92-103.
22. 22. Maggs, B., and Sitaraman, R. Simple algorithms for routing on butterfly networks with bounded queues. Proceedings of the Twenty Fourth Annual ACM Symposium on Theory of Computing. 1992, pp. 150-161.
23. 23. MP-1 family data-parallel computers. Technical report, MasPar Computer Corporation, 749 North Mary Ave., Sunnyvale, CA, 1987.
24. 24. Newman, I., and Schuster, A. Hot-potato algorithms for permutation routing. Technical Report PCL Report 9201, CS Department, Technion, 1992.
25. 25. Noakes, M., and Dally, W. System design of the J-Machine. Proceedings of the 6th MIT Conference on Advanced Research in VLSI. 1990, pp. 179-194.
26. 26. Rajasekaran, S., and Overholt, R. Constant queue routing on a mesh. J. Parallel Distrib. Comput. 15, 2 (June 1992), pp. 160-166.
27. 27. Ranade, A. Equivalence of message scheduling algorithms for parallel communication. Technical Report YALEU/DCS/TR-511, Department of Computer Science, Yale University, New Haven, CT, 1987.
28. 28. Seitz, C., Boden, N., Seizovic, J., and Su, W. The design of the Caltech Mosaic C multicomputer. Proceedings of the Symposium on Integrated Systems. 1993, pp. 1-22.