Design of a 3-D fully depleted SOI computational RAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 3, 2005, Pages 358-368

  Koob, John C ^a   Leder, Daniel A ^b   Sung, Raymond J ^c   Brandon, Tyler L ^a   Elliott, Duncan G ^a   Cockburn, Bruce F ^a   McIlrath, Lisa ^d  

^a UNIVERSITY OF ALBERTA   (Canada)

^b Edmonton ^*  (Canada)

^c BROADCOM CORPORATION   (United States)

^d R3 Logic Inc   (United States)

Author keywords

Memory architecture; Multiprocessor intercon nection; Parallel processing; Silicon on insulator (SOI) technology

Indexed keywords

BANDWIDTH; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; ROUTERS; SILICON ON INSULATOR TECHNOLOGY; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION NETWORKS;

GLOBAL ROUTING; MEMORY ARCHITECTURE; MULTIPROCESSOR INTERCONNECTION; PROCESSING ELEMENT;

RANDOM ACCESS STORAGE;

EID: 15844419782     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842890     Document Type: Article

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