Delay chain based programmable jitt+er generator

Proceedings - Ninth IEEE European Test Symposium, ETS 2004

Volumn , Issue , 2004, Pages 16-21

  Xia, Tian ^a   Song, Peilin ^b   Jenkins, Keith A ^b   Lo, Jien Chung ^c  

^a UNIVERSITY OF VERMONT   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF RHODE ISLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST EQUIPMENT (ATE); JITTER FREE SIGNAL; JITTER GENERATOR; PHASE DEVIATION; SPEED DIGITAL CIRCUITS;

BLOCK CODES; CALIBRATION; DIGITAL CIRCUITS; FAULT TOLERANT COMPUTER SYSTEMS; PHASE MODULATION; VOLTAGE CONTROL;

JITTER;

EID: 15844381598     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. ITU-T O.171 Timing Jitter and Wonder Measuring Equipment for Digital Systems.
2. International Technology Roadmap for Semiconductors 2003 Edition.
3. Crystal Semiconductor. Co. Application Note. "Jitter Testing Procedures for Compliance with AT&T 62411". http://www.crystal.com.
4. Masashi Shimanouchi, "An Approach to Consistent Jitter Modeling for Various Jitter Aspects and Measurement Methods", Proc, ITC, pp.848-857, 2001.
5. B.R.Veillette,G.W.Robert, "On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops", IEEE J.S.S.C, Vol.33, No.3, pp483-491, 1998.
6. R. Jacob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout and Simulation", A JOHN WILEY & SON, INC. Publication, 1997.
7. T.J. Yamaguchi, M.Soma, M. Ishida, T. Watanabe, T. Ohmi, "Extraction of peak-to-peak and RMS Sinusoidal Jitter Using An Analytic Signal Method", Proc, VTS, pp.395-402,April,2000.