Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2003, Pages 326-329

  Shimada, Hajime ^a   Ando, Hideki ^a   Shimada, Toshio ^a  

^a NAGOYA UNIVERSITY   (Japan)

Author keywords

Dynamic voltage scaling; Future process technology; Low power consumption; Pipeline stage

Indexed keywords

DYNAMIC VOLTAGE SCALING; FUTURE PROCESS TECHNOLOGY; LOW POWER CONSUMPTION; PIPELINE STAGE; FREQUENCY; LOW ENERGY CONSUMPTION; PERMISSION; PIPELINE STAGE UNIFICATION; POWER ENGINEERING AND ENERGIES; PROCESS GENERATION; REDUCE ENERGY CONSUMPTION; VARIABLE SUPPLY VOLTAGES;

COMPUTATIONAL METHODS; DATA STORAGE EQUIPMENT; ELECTRIC CLOCKS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; TRANSISTORS; CLOCKS; COMPUTER ARCHITECTURE; LOW POWER ELECTRONICS; PIPELINE PROCESSING SYSTEMS; PIPELINES; POWER ELECTRONICS; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

PROGRAM PROCESSORS; VOLTAGE SCALING;

EID: 1542329194     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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