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Volumn , Issue , 1999, Pages 105-109

Exploiting conditional instructions in code generation for embedded VLIW processors

Author keywords

[No Author keywords available]

Indexed keywords

CODE OPTIMIZATION TECHNIQUE; CODE PERFORMANCE; DYNAMIC PROGRAMMING TECHNIQUES; EMBEDDED PROCESSOR ARCHITECTURE; EMBEDDED PROCESSORS; MACHINE PROGRAMS; OPTIMAL SELECTION; WORST-CASE EXECUTION TIME;

EID: 15244352623     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761104     Document Type: Conference Paper
Times cited : (11)

References (10)
  • 2
    • 85027192248 scopus 로고
    • Automatic instruction code generation based on trellis diagrams
    • B. Wess: Automatic Instruction Code Generation based on Trellis Diagrams, IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 645-648
    • (1992) IEEE Int. Symp. on Circuits and Systems (ISCAS) , pp. 645-648
    • Wess, B.1
  • 3
    • 0029710317 scopus 로고    scopus 로고
    • Using register transfer paths in code generation for heterogeneous memory-register architectures
    • G. Araujo,S.Malik, M. Lee: Using Register Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures, 33rd Design Automation Conference (DAC), 1996
    • (1996) 33rd Design Automation Conference (DAC)
    • Araujo, G.1    Malik, S.2    Lee, M.3
  • 8
    • 0342363503 scopus 로고    scopus 로고
    • Introductionto predicated execution
    • Jan.
    • W. Hwu: Introductionto Predicated Execution, IEEE Computer, Jan. 1998, pp. 49-50
    • (1998) IEEE Computer , pp. 49-50
    • Hwu, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.