Optimizing architecture activity and logic depth for static and dynamic power reduction

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 41-44

  Pieuet, Christian ^a   Schuster, Christian ^b   Nagel, Jean Luc ^b  

^a CSEM   (Switzerland)

^b UNIVERSITY OF NEUCHÂTEL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY MULTIPLYING CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; THRESHOLD VOLTAGE; TRANSISTORS;

LEAKAGE POWER; LOW OPERATING POWER (LOP); LOW STANDBY POWER (LSTP) TECHNOLOGIES; POWER CONSUMPTION;

COMPUTER ARCHITECTURE;

EID: 14844307142     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Belleville, Olivier Faynot, "Evolution of deep submicron bulk and SOI technologies", Chapter 2, in "Low Power Electronics Design", edited by C. Piguet, CRC Press, will be published in July 2004.
2. C. Heer et al. "Designing low-power circuits: an industrial point of view", PATMOS 2001, Yverdon, September 26-28, 2001
3. C. Piguet et al. "Techniques de circuits et méthodes de conception pour réduire la consommation statique dans les technologies profondément submicroniques", Proc. FTFC'03, Paris, May 15-16, 2003, pp. 21-29
4. C. Piguet, V. Narayanan, "Guest Editorial", IEEE Trans. on VLSI Systems, Vol. 12, No 2 and No 3, 2004, February and March Issues.
5. Brodersen, R.W., et al., "Methods for True Power Minimization", Proc. Int'l Conf. on Computer Aided Design. San Jose, 2002, Nov., pp. 35-42
6. K. Nose, T. Sakurai, "Optimization of Vdd and Vth for Low-Power and High-Speed Applications", ASPDAC, January 2000, pp. 469-474.