Frequency domain filter using an accurate reconfigurable FFT/IFFT core

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 165-168

  Grandmaison, Marie Eve ^a   Belzile, Jean ^a   Thibeault, Claude ^a   Gagnon, François ^a  

^a ÉCOLE DE TECHNOLOGIE SUPÉRIEURE   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FAST FOURIER TRANSFORMS; FREQUENCY DOMAIN ANALYSIS; FREQUENCY MULTIPLYING CIRCUITS; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

DATA BLOCK PROCESSING; FILTER COEFFICIENTS; LINEAR DIGITAL FILTERING; SIGNAL TO QUANTIZATION NOISE RATIO (SQNR);

FIR FILTERS;

EID: 14844297093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M.-E. Grandmaison, J. Belzile, C. Thibeault, and F. Gagnon, "Reconfigurable and Efficient FFT/IFFT Architecture," Canadian Conference on Electrical and Computer Engineering, Niagara Falls, May 2004.
2. J. G. Proakis and D. G. Manolakis, Digital signal processing : principles, algorithms, and applications, 3rd ed. Upper Saddle River, N.J.: Prentice-Hall, 1996.
3. S. He and M. Torkelson, "A new approach to pipeline FFT processor," The 10th International Parallel Processing Symposium, pp 766-770, 1996.
4. Xilinx Inc. Virtex-II Pro platform FPGA user guide. Available: http://direct.xilinx.com/bvdocs/userguides/ug012.pdf.
5. J. G. Proakis, Digital communications, 3rd ed. New York, McGraw-Hill, 1995.