|
Volumn , Issue , 2004, Pages 61-64
|
Formal verification of a bus structure modeled in SystemC
|
Author keywords
[No Author keywords available]
|
Indexed keywords
BUS STRUCTURES;
MODEL CHECKING;
REGISTER-TRANSFER LEVEL (RTL);
SYSTEM LEVEL DESIGNS;
CODES (SYMBOLS);
COMPUTER HARDWARE;
COMPUTER SOFTWARE;
DIGITAL LIBRARIES;
GRAPHIC METHODS;
MATHEMATICAL MODELS;
OBJECT ORIENTED PROGRAMMING;
SYSTEMS ANALYSIS;
|
EID: 14844288439
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (1)
|
References (13)
|