메뉴 건너뛰기




Volumn , Issue , 2004, Pages 61-64

Formal verification of a bus structure modeled in SystemC

Author keywords

[No Author keywords available]

Indexed keywords

BUS STRUCTURES; MODEL CHECKING; REGISTER-TRANSFER LEVEL (RTL); SYSTEM LEVEL DESIGNS;

EID: 14844288439     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (13)
  • 2
  • 4
    • 0000963996 scopus 로고
    • Abstract interpretation frameworks
    • August
    • P. Cousot and R. Cousot. Abstract interpretation frameworks. Journal of Logic and Computation, 2(4):511-547, August 1992.
    • (1992) Journal of Logic and Computation , vol.2 , Issue.4 , pp. 511-547
    • Cousot, P.1    Cousot, R.2
  • 7
    • 0029697462 scopus 로고    scopus 로고
    • I'm done simulating: Now what? Verification coverage analysis and correctness checking of the DECchip21164 alpha microprocessor
    • M. Kantrowitz and L. Noack. I'm Done Simulating: Now What? Verifi cation Coverage Analysis and Correctness Checking of the DECchip21164 Alpha Microprocessor, In Proc. ACM/IEEE Design Automation Conference, 1996.
    • (1996) Proc. ACM/IEEE Design Automation Conference
    • Kantrowitz, M.1    Noack, L.2
  • 9
    • 0002755438 scopus 로고    scopus 로고
    • Integrating model checking into the semiconductor design fbw
    • March
    • P. C. Pixley. Integrating model checking into the semiconductor design fbw, Computer Design's Electronic Systems journal, pp. 67-74, March 1999.
    • (1999) Computer Design's Electronic Systems Journal , pp. 67-74
    • Pixley, P.C.1
  • 12
    • 84860102779 scopus 로고    scopus 로고
    • Systemc website: http://www.systemc.org, 2004.
    • (2004) Systemc Website


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.