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Volumn 45, Issue 12, 1996, Pages 1345-1355

A new approach to fixed-coefficient inner product computation over finite rings

Author keywords

Computer arithmetic; Digital signal processing; Inner product computation; Residue number system; VLSI design

Indexed keywords


EID: 1442308002     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.545965     Document Type: Article
Times cited : (6)

References (19)
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    • Bayoumi, M.A.1    Jullien, G.A.2    Miller, W.C.3
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    • (1988) IEEE J. Selected Areas of Comm. , vol.6 , pp. 504-512
    • Taheri, M.1    Jullien, G.A.2    Miller, W.C.3
  • 9
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    • An Efficient Bit-Level Systolic Cell Design for Finite Ring Digital Signal Processing Applications
    • G.A. Jullien, P.D. Bird, J.T. Carr et al., "An Efficient Bit-Level Systolic Cell Design for Finite Ring Digital Signal Processing Applications," J. VLSI Signal Processing, vol. 1, pp. 189-207,1989.
    • (1989) J. VLSI Signal Processing , vol.1 , pp. 189-207
    • Jullien, G.A.1    Bird, P.D.2    Carr, J.T.3
  • 10
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    • Improved Cellular Structures for BitSteered ROM Finite Ring Systolic Arrays
    • New Orleans, May 1-3
    • G.A. Jullien and W.C. Miller, "Improved Cellular Structures for BitSteered ROM Finite Ring Systolic Arrays," Proc. IEEE Int'l Symp. Circuits and Systems, pp. 1,415-1,417, New Orleans, May 1-3,1990.
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    • Jullien, G.A.1    Miller, W.C.2
  • 12
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  • 13
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    • Design of a Discrete Cosine Transform Circuit Using the Residue Number System
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    • (1993) Proc. European Conf. Design Automation , pp. 584-588
    • Wrzyszcz, A.1    Caban, D.2    Dagless, E.L.3
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  • 18
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    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 14-22
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  • 19
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    • G.A. Jullien, B. Erickson, and W.C. Miller, "RAM-JET: Towards the Removal of Multiplicative Complexity in Digital Signal Processing VLSI Architectures," Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 748-752, Pacific Grove, Calif., Oct. 31-Nov. 2, 1988.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.