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Volumn , Issue , 2004, Pages 16-21

A partial reconfigurable architecture for controllers based on Petri nets

Author keywords

FPGAs; Partial Reconfiguration; Petri Nets; Programmable Logic Controller (PLC); Virtual Hardware

Indexed keywords

COMPUTER HARDWARE; DIGITAL CONTROL SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; PETRI NETS; PROCESS CONTROL; PROGRAMMABLE LOGIC CONTROLLERS; REAL TIME SYSTEMS;

EID: 14244255060     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (22)

References (13)
  • 1
    • 0032273132 scopus 로고    scopus 로고
    • SFC, petri nets and application specific logic controllers
    • Adamski, Marian; "SFC, Petri Nets and Application Specific Logic Controllers", Proceedings of IEEE, 1998.
    • (1998) Proceedings of IEEE
    • Adamski, M.1
  • 2
    • 0032674941 scopus 로고    scopus 로고
    • Partitioning sequential circuits on dynamically reconfigurable FPGAs
    • June
    • Chang, Douglas; Sadowska, Marek; "Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs", IEEE Transactions on Computer, vol. 48, no. 6, June 1999.
    • (1999) IEEE Transactions on Computer , vol.48 , Issue.6
    • Chang, D.1    Sadowska, M.2
  • 4
    • 14244266457 scopus 로고    scopus 로고
    • Architectural design of RISC processor for programmable logic controllers
    • Sungwoo Resort, February
    • th CISL Winter Workshop, Sungwoo Resort, February 1996.
    • (1996) th CISL Winter Workshop
    • Koo, K.1
  • 5
    • 0024645936 scopus 로고
    • Petri nets: Properties, analysis and applications
    • April
    • Murata, Tadao; "Petri Nets: Properties, Analysis and Applications", Proceedings of the IEEE, vol. 77, no. 4, April 1989.
    • (1989) Proceedings of the IEEE , vol.77 , Issue.4
    • Murata, T.1
  • 6
    • 14244268453 scopus 로고    scopus 로고
    • Algorithm for switching context temporal partitioning based in CDFG-petri net model
    • Nascimento, Paulo S. B.; Lima, Manoel, E.; Maciel, Paulo R. M.; "Algorithm for Switching Context Temporal Partitioning Based in CDFG-Petri Net Model", Proceedings HPC2003, pp. 254-258.
    • Proceedings HPC2003 , pp. 254-258
    • Nascimento, P.S.B.1    Lima, M.E.2    Maciel, P.R.M.3
  • 7
    • 14244267556 scopus 로고    scopus 로고
    • Virtex II plataform FPGAs: Introduction and overview
    • September 26
    • Xilinx, Virtex II Plataform FPGAs: Introduction and Overview, Datasheet DS031-1 (v 1.9), September 26, 2002.
    • (2002) Datasheet DS031-1 (V 1.9)
  • 8
    • 14244262855 scopus 로고    scopus 로고
    • Virtex II plataform FPGAs: Detailed description
    • December 6
    • Xilinx, Virtex II Plataform FPGAs: Detailed Description, Datasheet DS031-2 (v 2.1.1), December 6, 2002.
    • (2002) Datasheet DS031-2 (V 2.1.1)
  • 9
    • 22444431905 scopus 로고    scopus 로고
    • Two flows for partial reconfiguration: Module based or small bit manipulations
    • May 17
    • Xilinx, Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, Application Notes XAPP290 (v 1.0), May 17, 2002.
    • (2002) Application Notes XAPP290 (V 1.0)
  • 10
    • 14244269286 scopus 로고    scopus 로고
    • Virtex II platform FPGA user guide
    • December 2
    • Xilinx, Virtex II Platform FPGA User Guide, User Guide UG002 (V 1.5) December 2, 2002.
    • (2002) User Guide UG002 (V 1.5)
  • 12
    • 14244258565 scopus 로고    scopus 로고
    • site for information of prices in November
    • www.marshall.com, site for information of prices in November 2003.
    • (2003)
  • 13
    • 14244267977 scopus 로고    scopus 로고
    • www.siemens.com/simatic-controller.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.