Novel state minimization and state assignment in finite state machine design for low-power portable devices

Integration, the VLSI Journal

Volumn 38, Issue 4, 2005, Pages 549-570

  Shiue, Wen Tsong ^a  

^a Oregon State University   (United States)

Author keywords

Finite state machine (FSM) synthesis and optimization; Heuristic algorithm; Low power design; Sequential circuit design; State assignment; State minimization

Indexed keywords

ALGORITHMS; BENCHMARKING; BOOLEAN ALGEBRA; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; CRITICAL PATH ANALYSIS; FINITE AUTOMATA; GRAPH THEORY; OPTIMIZATION; PORTABLE EQUIPMENT; STATE ASSIGNMENT;

FINITE STATE MACHINES (FSM); STATE ENCODING ALGORITHMS; STATE MINIMIZATION; SUM-OF-PRODUCT (SOP); SYSTEM SPECIFICATION;

MACHINE DESIGN;

EID: 14044268038     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.08.004     Document Type: Article

References (26)

1. Zvi Kohavi, Switching and Finite Automata Theory, nineteenth reprint, Tata Mcgraw-Hill, New Delhi, 1996, pp. 385-463.
2. J.E. Hopcroft An n log n algorithm for minimizing states in a finite automaton Z. Kohavi A. Paz Theory of Machines and Computations 1971 Academic Press New York 189 196
3. R.G. Bennets An improved method of prime C-class derivation in the state reduction of sequential networks IEEE Trans. Comput. C-20 1971 229 231
4. R.G. Bennets A computer algorithm for state-table reduction Radio Electron. Eng. 42 1972 513 520
5. T. Villa, and A. Sangiovanni-Vincentelli NOVA state assignment for optimal two-level logic implementation IEEE Trans. Comput. Aided Designs 9 9 1990 905 924
6. B. Lin, A.R. Newton, Synthesis of multiple level logic from symbolic high-level description languages, Proceedings of International Conference on VLSI, August 1989, pp. 187-196.
7. F. Hennie Finite State Models for Logical Machines 1968 Wiley pp. 140-175
8. L. Benini, and G. De Micheli State encoding for low power dissipation IEEE J. Solid-State Circuits 30 3 1995
9. S. Mitra, L. Avra, E. McCluskey, An output encoding problem and a solution technique, IEEE/ACM International Conference on Computer-Aided Design, 1997.
10. B. Iyer, M. Ciesielski, Reencoding for cycle-time minimization under fixed encoding length, International Conference on Computer-Aided Design, 1998.
11. C. Wang, and K. Roy An activity-driven encoding scheme for power optimization in microprogrammed control unit IEEE Trans. VLSI Systems 7 1 1999 130 134
12. I. Pomeranz, K. Cheng, State encoding using input/output functions, 29th ACM/IEEE Design Automation Conference, 1992, pp. 573-577.
13. J. Monteiro, A. Oliveira, Finite state machine decomposition for low power, Proceedings of the 35th Annual Conference on Design Automation, June 15-19, 1998, pp. 758-763.
14. A. Iranli, P. Rezvani, M. Pedram, Low power synthesis of state machines with mixed D and T flip flops, Asia South Pacific Design Automation Conference, January 2003.
15. E. Pastor, J. Cortadella, An efficient unique state coding algorithm for signal transition graphs, IEEE International Conference on Computer Design: VLSI in Computers & Processors, Cambridge, October 1993, pp. 174-177.
16. G. De Micheli, et al., Optimal state assignment for finite state machines, IEEE Trans. Comput. Aided Designs (1985) 269-285.
17. S. Devadas, et al., MUSTANG: state assignment of finite state machines targeting multi-level logic implementations, IEEE Trans. Comput. Aided Designs (1988) 1290-1300.
18. S. Chow, Y Ho, T. Hwang, C. Liu, Low power realization of finite state machines, Proceedings of the 35th Annual Conference on Design Automation, 1998, pp. 758-763.
19. C.-Y. Tsui, M. Pedram, and A.M. Despain Low power state assignment targeting two and multilevel logic implementations IEEE Trans. Comput. Aided Designs 17 12 1998 1281 1291
20. L. Benini, and G. De Micheli State encoding for low power dissipation IEEE J. Solid-State Circuits 30 3 1995
21. S. Devadas, A.R. Newton, Exact algorithms for output encoding, state assignment and four-level Boolean minimization, International Conference on System Sciences, January 1990, pp. 387-396.
22. R. Brayton, F. Somenzi, Minimization of Boolean relations, International Symposium on Circuits and Systems, May 1989, pp. 738-743.
23. T.A. Dolotta, and E.J. McCluskey The coding of internal states of sequential circuits IRE Trans. Electron. Comput. 13 1964 549 562
24. T. Corman, C. Lesiserson, and R. Rivest Introduction to Algorithms 2001 MIT Press Cambridge, MA
25. K. Thulasiraman, and M. Swamy Graphs Theory and Algorithms 1992 Wiley-Interscience New York
26. G. Micheli Synthesis and Optimization of Digital Circuits 1994 Mc-Graw-Hill New York