VERTAF: An application framework for the design and verification of embedded real-time software

IEEE Transactions on Software Engineering

Volumn 30, Issue 10, 2004, Pages 656-674

  Hsiung, Pao Ann ^a   Lin, Shang Wei ^a   Tseng, Chih Hao ^a   Lee, Trong Yen ^b   Fu, Jih Ming ^c   See, Win Bin ^d  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^c CHENG SHIU UNIVERSITY   (Taiwan)

^d AEROSPACE INDUSTRIAL DEVELOPMENT CORPORATION   (Taiwan)

Author keywords

Application framework; Code generation; Embedded real time software; Formal synthesis; Formal verification; Scheduling; Software components; UML modeling

Indexed keywords

APPLICATION FRAMEWORK; CODE GENERATION; EMBEDDED REAL TIME SOFTWARE; FORMAL SYNTHESIS; FORMAL VERIFICATION; SOFTWARE COMPONENTS;

COMPUTER SIMULATION LANGUAGES; COMPUTER SOFTWARE REUSABILITY; EMBEDDED SYSTEMS; OBJECT ORIENTED PROGRAMMING; REAL TIME SYSTEMS;

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 14044266879     PISSN: 00985589     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSE.2004.68     Document Type: Article

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