Implementation of multiple-valued flip-flips using pass transistor logic

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Volumn , Issue , 2004, Pages 603-606

  Babu, Hafiz Md Hasan ^a   Zaber, Moinul Islam ^a   Rahman, Md Mazder ^a   Islam, Md Rafiquil ^a  

^a UNIVERSITY OF DHAKA   (Bangladesh)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; DIGITAL DEVICES; DIGITAL STORAGE; ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); SIGNAL ENCODING; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

BINARY FLIP-FLOPS; DIGITAL MEMORY UNITS; DIGITAL SYSTEMS; ELECTRONIC LATCHING CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 13944276740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Okihiko Ishuzuka, IEEE Trans, 1986, Synthesis of a Pass Transistor Network Applied to Multi-Valued Logic.
2. Etiemble, D., and Israel, M., IEEE trans, 1980,on the realization of multiple-valued flip-flops.
3. Sasao.T., IEEE Trans, April, 1998, Multiple-valued logic and optimization of programmable logic arrays.
4. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, IEEE JSSC, vol. 25. no. 2, April 1990, A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic.
5. A. P. Chandrakasan, S. Sheng, and R.W. Brodersen, IEEE JSSC, vol. SC-20, 1985,Low Power CMOS Digital Design.
6. N. Zhuang , H. Wu, Electronics Letters, Vol. 26,No.15, pp.1145-1146,1990,Novel ternary JKL flip lop.
7. J.I Accha. J.L Huertas, Electronics Letter, Vol.11, P. 624,1975,General Excitation table for a JK multistage.