Reconfigurable on-chip SIMD processor architectures for intelligent CMOS camera chips

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Volumn , Issue , 2004, Pages 251-255

  Fey, Dietmar ^a   Hoppe, Lutz ^a   Loos, Andreas ^a  

^a FRIEDRICH SCHILLER UNIVERSITY JENA   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; COMPUTER SIMULATION; HIGH SPEED CAMERAS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PHOTODETECTORS; REAL TIME SYSTEMS;

DATA RATES; GRIPPER ARMS; SERIAL ARCHITECTURE; SINGLE INSTRUCTION MULTIPLE DATA (SIMD) PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 13944258978     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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