Algorithm partitioning including optimized data-reuse for processor arrays

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Volumn , Issue , 2004, Pages 85-90

  Siegel, Sebastian ^a   Merker, Renate ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CACHE MEMORY; CONFORMAL MAPPING; DATABASE SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; FUNCTIONS; MATHEMATICAL OPERATORS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; SCHEDULING; SET THEORY; TWO DIMENSIONAL;

AFFINE INDEXED ALGORITHMS (AIA); FILTER COEFFICIENTS; PROCESSING ELEMENTS (PE); PROCESSOR ARRAYS;

PROGRAM PROCESSORS;

EID: 13944258476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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