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Volumn , Issue , 2004, Pages 363-370

Mixed synchronous/asynchronous state memory for low power FSM design

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ENERGY MANAGEMENT; FLIP FLOP CIRCUITS; LOGIC GATES; OPTIMIZATION; PROBLEM SOLVING; SWITCHING;

EID: 13944256596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dsd.2004.1333298     Document Type: Conference Paper
Times cited : (17)

References (10)
  • 4
    • 0028728145 scopus 로고
    • Saving power by synthesizing gated clocks for sequential circuits
    • L. Benini, P. Siegel, and G. De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits," IEEE Deisgn and Test of Computers, 1994, vol. 11, pp. 32-41.
    • (1994) IEEE Deisgn and Test of Computers , vol.11 , pp. 32-41
    • Benini, L.1    Siegel, P.2    De Micheli, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.