Checkpoint Processing And Recovery: An Efficient, Scalable Alternative to Reorder Buffers

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 11-19

  Akkary, Haitham ^a   Rajwar, Ravi ^b   Srinivasan, Srikanth T ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHECKPOINT PROCESSING AND RECOVERY (CPR); MICROARCHITECTURE;

BENCHMARKING; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA RECORDING; SCHEDULING; SYSTEMS ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 1342303764     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261382     Document Type: Review

References (7)

1. H. Akkary, R. Rajwar, and S.T. Srinivasan, "Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors," Proc. 36th Ann. Int'l Symp. Microarchitecture, ACM Press, 2003, p. 423-434.
2. J.E. Smith and A.R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors," Proc. 12th Ann. Int'l Symp. Computer Architecture, ACM Press, 1985, pp. 36-44.
3. W.W. Hwu and Y.N. Patt, "Checkpoint Repair For Out-Of-Order Execution Machines," Proc. 14th Ann. Int'l Symp. Computer Architecture, 1 Press, 1987, pp. 18-26.
4. E. Jacobson, E. Rotenberg, and J.E. Smith, "Assigning Confidence to Conditional Branch Predictions," Proc. 29th Int'l Symp. Microarchitecture, ACM Press, 1996, pp. 142-152.
5. M. Moudgill, K. Pingali, and S. Vassiliadis, "Register Renaming and Dynamic Speculation: an Alternative Approach," Proc. 26th Int'l Symp. Microarchitecture, ACM Press, 1993, pp. 202-213.
6. B. Bloom, "Space/Time Tradeoffs in Hash Coding with Allowable Errors," Comm. ACM, vol. 13, no. 7, July 1970, pp. 422-426.
7. A. Moshovos and G. Sohi, "Streamlining Inter-Operation Memory Communication via Data Dependence Prediction," Proc. 30th Int'l Symp. Microarchitecture, ACM Press, 1997, p.p. 235-245.