Using cutwidth to improve symbolic simulation and Boolean satisfiability

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 165-170

  Wang, Dong ^a   Clarke, E ^a   Zhu, Yunshan ^b   Kukula, J ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; RECONFIGURABLE HARDWARE;

BOOLEAN SATISFIABILITY; MEMORY REQUIREMENTS; NEW APPROACHES; SAT INSTANCES; SYMBOLIC SIMULATION; TIME COMPLEXITY; VARIABLE ORDERING; VERIFICATION TECHNIQUES;

MODEL CHECKING;

EID: 13244299516     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972824     Document Type: Conference Paper

References (15)

1. F. Aloul, I. Markov, and K. Sakallah. Faster SAT and Smaller BDDs via Common Function Structure. In Proc. of the International Conference on Computer Aided Design (ICCAD), 2001.
2. C.Leonard Berman. Circuit Width, Register Allocation, and Ordered Binary Decision Diagrams. IEEE Transactions on Computer-Aided Design 4(1), pages 1059-1066, August 1991.
3. R. E. Bryant. Symbolic Simulation-Techniques and Applications. In 27th Design Automation Conference, pages 517-521, June 1990.
4. Edmund M. Clarke, Orna Grumberg, and Doron Peled. Model Checking. MIT Press, 1999.
5. A.E. Dunlop and B.W. Kernighan. A Procedure for Placment of Standard Cell VLSI Circuits. IEEE Transactions on Computer-Aided Design 4(1), pages 92-98, 1985.
6. David FERNANDEZ-BACA. Nonserial Dynamic Programming Formulations of Satisfiability. Information Processing Letters 27, pages 323-326, May 1988.
7. George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. Multilevel Hypergraph Partitioning: Applications in VLSI Domain. In 34th ACM/IEEE Design Automation Conference, 1997.
8. K. L. McMillan. Symbolic Model Checking: An Approach to the State Explosion Problem. PhD thesis, Carnegie Mellon University, Computer Science Department, 1992.
9. In-Ho Moon and Fabio Somenzi. Border-Block Triangular Form and Conjunction Schedule in Image Computation. In Proceedings of the Formal Methods in Computer Aided Design (FMCAD), November 2000.
10. Matthew Moskewicz, Conor Madigan, Ying Zhao, Lintao Zhang, and Sharad Malik. Chaff: Engineering an Efficient SAT Solver. In 38th ACM/IEEE Design Automation Conference(DAC), June 2001.
11. David A. Plaisted, Armin Biere, and Yunshan Zhu. A Satisfiability Tester for Quantified Boolean Formulae. Submitted.
12. Mukul Prasad, Philip Chong, and Kurt Keutzer. Why is ATPG easy? In 36th ACM/IEEE Design Automation Conference(DAC), pages 22-28, October 1999.
13. J.P. Marques Silva and Karem A. Sakallah. GRASP - A New Search Algorithm for Satisfiability. In Proceedings of the IEEE international Conference on Computer Aided Design (ICCAD), pages 220-227, 1996.
14. Laurent Simon. The SAT-Ex Site. http://www.lri.fr/ simon/satex/satex.php3.
15. M.N. Velev. Superscalar Suite 1.0a. Available from: http://www.ece.cmu.edu/ mvelev.