Adding testability to an asynchronous interconnect for GALS SoC

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 20-23

  Efthymiou, Aristides ^a   Bainbridge, John ^a   Edwards, Douglas A ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAM LISTINGS; DESIGN FOR TESTABILITY; FEEDBACK; INTEGRATED CIRCUITS; SIGNAL ENCODING; STANDARDS;

ASYNCHRONOUS CIRCUITS; BOUNDARY LATCHES; TEST COVERAGE; TEST PATTERNS;

MICROPROCESSOR CHIPS;

EID: 13244281565     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. W. J. Bainbridge and S. B. Furber, "CHAIN: A delay insensitive CHip Area INterconnect," IEEE Micro, vol. 22, no. 5, pp. 16-23, Sept/Oct 2002.
2. K. van Berkel, A. Peelers, and F. te Beest, "Adding synchronous and LSSD modes to asynchronous circuits," in Proceedings of the International Symposium on Asynchronous Circuits and Systems, Apr. 2002, pp. 146-155.