Realizable reduction of interconnect circuits including self and mutual inductances

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 2, 2005, Pages 271-277

  Amin, Chirayu S ^a   Chowdhury, Masud H ^a   Ismail, Yehea I ^a  

^a Northwestern University   (United States)

Author keywords

Circuit; Circuit reduction; Estimation; Interconnect; Model order reduction (MOR); Simulation; Timing verification; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; FREQUENCIES; INDUCTANCE; PROBLEM SOLVING; TRANSFER FUNCTIONS; VLSI CIRCUITS;

CIRCUIT REDUCTION; INTERCONNECT; MODEL ORDER REDUCTION (MOR); TIMING VERIFICATION;

CIRCUIT THEORY;

EID: 13144295052     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.840545     Document Type: Article

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