Fractal engine

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3021, Issue , 1997, Pages 88-99

  Fatemi, O ^a   Panchanathan, S ^a  

^a UNIVERSITY OF OTTAWA   (Canada)

Author keywords

Affine transforms and video processors; Fractal block processing; VHDL; VLSI implementation

Indexed keywords

AFFINE TRANSFORMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE; ENGINES; FRACTALS; FREQUENCY DOMAIN ANALYSIS; FREQUENCY ESTIMATION; MOTION ESTIMATION;

BLOCK PROCESSING; CONTRAST ENHANCEMENT; IMAGE AND VIDEO PROCESSING; PIPELINED ARCHITECTURE; PROPOSED ARCHITECTURES; VHSIC HARDWARE DESCRIPTION LANGUAGES; VIDEO PROCESSOR; VLSI IMPLEMENTATION;

VIDEO SIGNAL PROCESSING;

EID: 12944324971     PISSN: 0277786X     EISSN: 1996756X     Source Type: Conference Proceeding    
DOI: 10.1117/12.263529     Document Type: Conference Paper

References (4)

1. A. E. Jacquin", Fractal Image Coding: A Review", Proceeding of the IEEE; vol. 81, No. 10, pp. 1451-1465, October 1993
2. M. F. Barnsley and S. Demko, "Iterated function systems and the global construction of fractals", Proc. Roy. Soc. London, vol. A399, pp. 243-275, 1985.
3. O. Fatemi and S. Panchanathan, "VLSI Chip-Set for Affine Based Video Compression"
4. O. Fatemi and S. Panchanathan, "FPGA Implementation Of A Matrix Transposer", June 1994, Proc. Canadian Workshop on Field-Programmable Devices pp. 4.4.1-4.4.7, Kingston, Canada.