Practical measurement of timing jitter contributed by a clock-and-data recovery circuit

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 1, 2005, Pages 119-126

  Pease, Christopher ^a   Babić, Dubravko ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b Etanvie Technologies   (United States)

Author keywords

Clock and data recovery (CDR); Contributed jitter; Jitter measurement; Jitter tolerance (JT); Random and deterministic jitter; Serializer deserializer (SERDES)

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; ERROR DETECTION; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK-AND-DATA RECOVERY (CDR) CIRCUIT; CONTRIBUTED JITTER; JITTER MEASUREMENT; JITTER TOLERANCE (JT); RANDOM-AND-DETERMINISTIC JITTER; SERIALIZER DESERIALIZER (SERDES) CHIPS;

TIMING JITTER;

EID: 12944287798     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838260     Document Type: Article

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