Low-k materials etch and strip optimization for sub 0.25μm technology

Proceedings of the IEEE 1999 International Interconnect Technology Conference, IITC 1999

Volumn , Issue , 1999, Pages 53-55

  Gao, T ^a   Gray, W D ^c   Van Hove, M ^a   Rosseel, E ^a   Struyf, H ^a   Meynen, H ^d   Vanhaelemeersch, S ^a   Maex, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c IMEC for Dow Corning   (Belgium)

^d Dow Corning SA Belgium   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DIELECTRIC MATERIALS; INTEGRATED CIRCUIT INTERCONNECTS;

ELECTRICAL PERFORMANCE; INTEGRATED CHIPS; INTER-METAL DIELECTRIC LAYERS; INTERCONNECT PERFORMANCE; MATERIAL DEGRADATION; MEASUREMENT METHODS; SENSITIVE PARAMETER; SINGLE DAMASCENE;

LOW-K DIELECTRIC;

EID: 12844277035     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1999.787076     Document Type: Conference Paper

References (2)

1. H. Meynen, et al., ECS 1998, Proc. Vol 98-3, pp. 29-42
2. T. Gao, et al., Proc. 1998 IITC, pp. 45-47