Enabling cache coherency for N-way SMP systems on programmable chips

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Volumn , Issue , 2004, Pages 312-

  Hung, Austin ^a   Bishop, William ^a   Kennings, Andrew ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; MULTIPROCESSING PROGRAMS; PROBLEM SOLVING; PROGRAM PROCESSORS;

CACHE COHERENCY MODULE (CCM); ON-CHIP-MEMORY; PROGRAMMABLE CHIPS; SYSTEM-ON-PROGRAMMABLE-CHIP (SOPC);

MICROPROCESSOR CHIPS;

EID: 12744269895     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Altera Corporation, San Jose, California. Avalon Bus Specification Reference Manual, July 2003.