-
1
-
-
0033720597
-
Hardware-software Co-design of embedded reconfigurable architectures
-
Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, "Hardware-Software Co-Design of Embedded Reconfigurable Architectures", ACM/IEEE Design Automation Conference (DAC), 2000, pp. 507-512.
-
(2000)
ACM/IEEE Design Automation Conference (DAC)
, pp. 507-512
-
-
Li, Y.1
Callahan, T.2
Darnell, E.3
Harr, R.4
Kurkure, U.5
Stockwood, J.6
-
2
-
-
0034848108
-
Integrating scheduling and physical design into coherent compilation cycle for reconfigurable computing architectures
-
K. Bazargan, S. Ogrenci, and M. Sarrafeadeh, "Integrating Scheduling and Physical Design into Coherent Compilation Cycle for Reconfigurable Computing Architectures", ACM/IEEE Design Automation Conference (DAC), 2001, pp. 635-640.
-
(2001)
ACM/IEEE Design Automation Conference (DAC)
, pp. 635-640
-
-
Bazargan, K.1
Ogrenci, S.2
Sarrafeadeh, M.3
-
3
-
-
12444259751
-
HW/SW partitioning approach for reconfigurable systems design
-
K. B. Chehida and M. Auguin, "HW/SW Partitioning Approach for Reconfigurable Systems Design", International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2002, pp. 247-251.
-
(2002)
International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES)
, pp. 247-251
-
-
Chehida, K.B.1
Auguin, M.2
-
5
-
-
79955155845
-
Partially reconfigurable cores for Xilinx Virtex
-
M. Dyer, C. Plessl, and M. Platzner, "Partially Reconfigurable Cores for Xilinx Virtex", International Conference on Field-Programmable Logic and Applications (FPL), 2002, pp. 292-301.
-
(2002)
International Conference on Field-programmable Logic and Applications (FPL)
, pp. 292-301
-
-
Dyer, M.1
Plessl, C.2
Platzner, M.3
-
6
-
-
84949777938
-
Configuration caching techniques for FPGA
-
Z. Li, K. Compton, and S. Hauck, "Configuration Caching Techniques for FPGA", IEEE International Symposium on Field-Programmable Gate Arrays (FPGA), 2000, pp. 22-36.
-
(2000)
IEEE International Symposium on Field-programmable Gate Arrays (FPGA)
, pp. 22-36
-
-
Li, Z.1
Compton, K.2
Hauck, S.3
-
8
-
-
0032668914
-
Embedded tutorial: Reconfigurable computing: What, why, and implications for design automation
-
A. DeHon and J. Wawrzynek, "Embedded Tutorial: Reconfigurable Computing: What, Why, and Implications for Design Automation", ACM/IEEE Design Automation Conference (DAC), 1999, pp. 610-615.
-
(1999)
ACM/IEEE Design Automation Conference (DAC)
, pp. 610-615
-
-
Dehon, A.1
Wawrzynek, J.2
-
9
-
-
0000950606
-
The roles of FPGAs in reprogrammable systems
-
S. Hauck, "The Roles of FPGAs in Reprogrammable Systems", Proceedings of the IEEE, 1998, 86(4): 615-638.
-
(1998)
Proceedings of the IEEE
, vol.86
, Issue.4
, pp. 615-638
-
-
Hauck, S.1
-
10
-
-
0031645164
-
Fast module mapping and placement for datapaths in FPGAs
-
T. J. Callahan, P. Chong, A. DeHon, and J. Wawrzynek, "Fast Module Mapping and Placement for Datapaths in FPGAs", International Symposium on Field-Programmable Gate Arrays (FPGA), 1998., pp. 123-132.
-
(1998)
International Symposium on Field-programmable Gate Arrays (FPGA)
, pp. 123-132
-
-
Callahan, T.J.1
Chong, P.2
Dehon, A.3
Wawrzynek, J.4
-
11
-
-
0035014386
-
ENISLE: An intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning
-
S. -W. Cheng and K. -H. Cheng, "ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning", International Symposium on Circuits and Systems (ISCAS), 2001, pp. 167-170.
-
(2001)
International Symposium on Circuits and Systems (ISCAS)
, pp. 167-170
-
-
Cheng, S.W.1
Cheng, K.H.2
-
12
-
-
0344704289
-
A survey of layout problems
-
Sept.
-
J. Diaz, J. Petit, and M. Serna, "A Survey of Layout Problems", ACM Computing Surveys, Sept. 2002, pp. 313-356.
-
(2002)
ACM Computing Surveys
, pp. 313-356
-
-
Diaz, J.1
Petit, J.2
Serna, M.3
-
13
-
-
12444304466
-
Remote and partial reconfiguration of FPGAs: Tools and trends
-
D. Mesquita, F. Moraes, J. Palma, L. Moller, and N. Calazans, "Remote and Partial Reconfiguration of FPGAs: Tools and Trends", Reconfigurable Architectures Workshop (RAW), 2003.
-
(2003)
Reconfigurable Architectures Workshop (RAW)
-
-
Mesquita, D.1
Moraes, F.2
Palma, J.3
Moller, L.4
Calazans, N.5
-
16
-
-
0041633687
-
Global resource sharing for synthesis of control data flow graphs on FPGAs
-
S. O. Memik, G. Memik, R. Jafari, and E. Kursun, "Global Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs", ACM/IEEE Design Automation Conference (DAC), 2003, pp. 604-609.
-
(2003)
ACM/IEEE Design Automation Conference (DAC)
, pp. 604-609
-
-
Memik, S.O.1
Memik, G.2
Jafari, R.3
Kursun, E.4
-
17
-
-
0036957219
-
Datapath merging and interconnection sharing for reconfigurable architectures
-
N. Moreano, G. Araujo, Z. Huang, and S. Malik, "Datapath Merging and Interconnection Sharing for Reconfigurable Architectures", International Symposium on System Synthesis (ISSS), 2002, pp. 38-43.
-
(2002)
International Symposium on System Synthesis (ISSS)
, pp. 38-43
-
-
Moreano, N.1
Araujo, G.2
Huang, Z.3
Malik, S.4
-
19
-
-
84860090901
-
-
http://amalfi.dis.unina.it/graph/db/vflib-2.0/doc/vflib.html
-
-
-
-
20
-
-
84860081683
-
-
www-3.ibm.com/chips/products/asics/products/cores/efpga.html
-
-
-
-
21
-
-
84860083411
-
-
http://www.xilinx.com/products/tables/fpga.htm#v2p
-
-
-
-
22
-
-
84860081682
-
-
http://www.research.philips.com/InformationCenter/Global/FArticleSummary. asp?lNodeId-931#ambintel
-
-
-
-
23
-
-
84860088773
-
-
http://research.microsoft.com/easyliving/
-
-
-
-
24
-
-
84860081681
-
-
http://architecture.mit.edu/house_n/
-
-
-
-
25
-
-
84860081680
-
-
http://www.awarehome.gatech.edu/
-
-
-
-
26
-
-
84860081685
-
-
http://www.qstech.com/tech_products.htm
-
-
-
-
27
-
-
84860083412
-
-
http://www.picochip.com/
-
-
-
-
28
-
-
84860083413
-
-
http://www.xilinx.com/apps/epld.htm#CoolRunner
-
-
-
-
29
-
-
84860081684
-
-
http://www.xilmx.com/publications/products/sp2e/wp_pdf/wp153.pdf
-
-
-
-
30
-
-
84860081679
-
-
http://www.ece.umn.edu/users/ababei
-
-
-
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