Passivation Layers for Reduced Total Dose Effects and ELDRS in Linear Bipolar Devices

IEEE Transactions on Nuclear Science

Volumn 50, Issue 6 I, 2003, Pages 1784-1790

  Shaneyfelt, Marty R ^a   Pease, Ronald L ^b   Maher, Michael C ^c   Schwank, James R ^a   Gupta, Sunny ^c   Dodd, Paul E ^a   Riewe, Leonard C ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b RLP Research   (United States)

^c NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Bipolar linear integrated circuits; Enhanced low dose rate sensitivity; Hardness assurance testing; Integrated circuit reliability; Integrated circuit testing; Mechanical stress; Passivation layers; Pre irradiation elevated temperature stress

Indexed keywords

DOSIMETRY; HYDROGEN; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; OXIDES; PASSIVATION; RADIATION EFFECTS; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; STRESS ANALYSIS; THERMAL CYCLING; THERMAL STRESS;

BIPOLAR LINEAR INTEGRATED CIRCUITS; ENHANCED LOW-DOSE-RATE SENSITIVITY; HARDNESS ASSURANCE TESTING; INTEGRATED CIRCUIT RELIABILITY; MECHANICAL STRESS; PASSIVATION LAYERS; PRE-IRRADIATION ELEVATED TEMPERATURE STRESS; RADIATION HARDENING (ELECTRONICS); RADIATION RESPONSE; THERMAL STRESS EFFECTS;

BIPOLAR SEMICONDUCTOR DEVICES;

EID: 1242310332     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.820771     Document Type: Conference Paper

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