A three-dimensional MOS transistor formation technique with crystallographic orientation-dependent TMAH etchant

Sensors and Actuators, A: Physical

Volumn 111, Issue 2-3, 2004, Pages 310-316

  Sunami, Hideo ^a   Furukawa, Tomoyasu ^a,b   Masuda, Taiyo ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Corrugated channel transistor; Orientation dependent etching; TMAH; 1 1 0 Silicon substrate, three dimensional structure

Indexed keywords

ANISOTROPY; CRYSTALLOGRAPHY; DYNAMIC RANDOM ACCESS STORAGE; ETCHING; SILICON; SINGLE CRYSTALS;

CORRUGATED-CHANNEL TRANSISTORS; ORIENTATION-DEPENDENT ETCHING; SILICON SUBSTRATES; TETRA METHYL AMMONIUM HYDROXIDE (TMAH);

MOSFET DEVICES;

EID: 1242298507     PISSN: 09244247     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sna.2003.10.081     Document Type: Article

References (10)

1. D.L. Kendall, W.T. Matzen, Large Value Capacitor, US Patent 3962713 (1973).
2. H. Sunami, Field-effect transistor, Jpn. Patent 13443866 (1975).
3. Sunami H., Kure T., Hashimoto N., Toyabe T., Asai S. A corrugated capacitor cell (CCC) for megabit dynamic MOS memories. IEEE Electron. Device Lett. 4:1983;90-91.
4. Sunami H., Kure T., Hashimoto N., Toyabe T., Asai S. A corrugated capacitor cell (CCC). IEEE Trans. Electron. Devices. 31:1984;746-753.
5. Koyanagi M., Sunami H., Hashimoto N. Novel high density, stacked capacitor MOS RAM, Suppl. Jpn. J. Appl. Phys. 18(1):1979;35-42.
6. Hisamoto D., Kaga T., Takeda E. Impact of the vertical SOI "DELTA" structure on planar device technology. IEEE Trans. Electron. Devices. 38:1991;1419-1424.
7. Y.-K. Cho, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, C. Hu, Sub-20 nm CMOS FinFET technologies, Technical Digest of IEEE International Electronic Devices Meeting, Washington, DC, USA, 2-5 December 2001.
8. T. Furukawa, H. Yamashita, H. Sunami, Corrugated-channel transistor (CCT) for area-conscious applications, in: Proceedings of the International Conference on Solid State Devices and Materials, Nagoya, Japan, 17-19 September 2002.
9. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai, Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration, Custom Integrated Circuits Conference, Florida, USA, 21-24 May 2000.
10. Mutoh S., Douseki T., Matsuya Y., Aoki T., Shigematsu S., Yamada J. 1-V power supply high-speed digital circuit technology with multithreshold-volgate CMOS. IEEE J. Solid State Circuits. 30:1995;847.