-
3
-
-
84976725287
-
Software pipelining
-
September
-
Vicki H. Allan, Reese B. Jones, Randal M. Lee, and Stephen I. Allan. Software pipelining. ACM Computing Surveys, 27(3):367-432, September 1995.
-
(1995)
ACM Computing Surveys
, vol.27
, Issue.3
, pp. 367-432
-
-
Allan, V.H.1
Jones, R.B.2
Lee, R.M.3
Allan, S.I.4
-
5
-
-
0002626826
-
SSA is functional programming
-
April
-
Andrew W. Appel. SSA is functional programming. ACM SIGPLAN Notices, April 1998.
-
(1998)
ACM SIGPLAN Notices
-
-
Appel, A.W.1
-
6
-
-
0011804159
-
C for system level design
-
Munich, Germany, March
-
Guido Arnout. C for system level design. In Design, Automation and Test in Europe (DATE), pages 384-387, Munich, Germany, March 1999.
-
(1999)
Design, Automation and Test in Europe (DATE)
, pp. 384-387
-
-
Arnout, G.1
-
9
-
-
0033488498
-
Parallelizing applications into silicon
-
Jonathan Babb, Martin Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank Rajeev Barua, and Saman Amarasinghe. Parallelizing applications into silicon. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 1999.
-
(1999)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
-
-
Babb, J.1
Rinard, M.2
Moritz, C.A.3
Lee, W.4
Frank, M.5
Barua, R.6
Amarasinghe, S.7
-
10
-
-
0032206398
-
Clocking design and analysis for a 600-MHz Alpha microprocessor
-
November
-
Daniel W. Bailey and Bradley J. Benschneider. Clocking design and analysis for a 600-MHz Alpha microprocessor. IEEE Journal of Solid-State Circuits, 33(11):1627, November 1998.
-
(1998)
IEEE Journal of Solid-state Circuits
, vol.33
, Issue.11
, pp. 1627
-
-
Bailey, D.W.1
Benschneider, B.J.2
-
12
-
-
12344320297
-
VLSI programming of asynchronous circuits for low power
-
Graham Birtwistle and Al Davis, editors, Workshops in Computing Springer Verlag
-
Kees van Berkel and Martin Rem. VLSI programming of asynchronous circuits for low power. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 152-210. Springer Verlag, 1995. summary at www.cse.ttu.edu.tw/cheng/courses/soc/S02/AsyncSoc08.ppt; also Nat.Lab, Technical Note Nr. UR 005/94, Philips Research Laboratories, Eindhoven, the Netherlands.
-
(1995)
Asynchronous Digital Circuit Design
, pp. 152-210
-
-
Van Berkel, K.1
Rem, M.2
-
13
-
-
12344318271
-
-
Philips Research Laboratories, Eindhoven, the Netherlands
-
Kees van Berkel and Martin Rem. VLSI programming of asynchronous circuits for low power. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 152-210. Springer Verlag, 1995. summary at www.cse.ttu.edu.tw/cheng/courses/soc/S02/AsyncSoc08.ppt; also Nat.Lab, Technical Note Nr. UR 005/94, Philips Research Laboratories, Eindhoven, the Netherlands.
-
Nat. Lab, Technical Note Nr. UR 005/94
, vol.UR 005-94
-
-
-
14
-
-
0003567872
-
-
Kluwer Academic Publishers, Boston, MA
-
R. Brayton, A. Sangiovanni-Vincentelli, G. Hachtel, and C. McMullin. Logic Minimization Algorithms for Digital Circuits, Kluwer Academic Publishers, Boston, MA, 1984.
-
(1984)
Logic Minimization Algorithms for Digital Circuits
-
-
Brayton, R.1
Sangiovanni-Vincentelli, A.2
Hachtel, G.3
McMullin, C.4
-
17
-
-
12344328498
-
-
PhD thesis, Carnegie Mellon University, Computer Science Department, December. Technical report CMU-CS-03-217
-
Mihai Budiu. Spatial Computation. PhD thesis, Carnegie Mellon University, Computer Science Department, December 2003. Technical report CMU-CS-03-217.
-
(2003)
Spatial Computation
-
-
Budiu, M.1
-
20
-
-
12344264898
-
Inter-iteration scalar replacement in the presence of conditional control-flow
-
Carnegie Mellon University, Department of Computer Science
-
Mihai Budiu and Seth Copen Goldstein. Inter-iteration scalar replacement in the presence of conditional control-flow. Technical Report CMU-CS-04-103, Carnegie Mellon University, Department of Computer Science, 2004.
-
(2004)
Technical Report
, vol.CMU-CS-04-103
-
-
Budiu, M.1
Goldstein, S.C.2
-
21
-
-
12344269990
-
Peer-to-peer hardware-software interfaces for reconfigurable fabrics
-
Napa Valley, CA, April
-
Mihai Budiu, Mahim Mishra, Ashwin Bharambe, and Seth Copen Goldstein. Peer-to-peer hardware-software interfaces for reconfigurable fabrics. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 57-66, Napa Valley, CA, April 2002.
-
(2002)
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
, pp. 57-66
-
-
Budiu, M.1
Mishra, M.2
Bharambe, A.3
Goldstein, S.C.4
-
22
-
-
0002986475
-
The SimpleScalar tool set, version 2.0
-
ACM SIGARCH, June
-
Doug Burger and Todd M. Austin. The SimpleScalar tool set, version 2.0. In Computer Architecture News, volume 25, pages 13-25. ACM SIGARCH, June 1997.
-
(1997)
Computer Architecture News
, vol.25
, pp. 13-25
-
-
Burger, D.1
Austin, T.M.2
-
23
-
-
84956862926
-
Instruction level parallelism for reconfigurable computing
-
Hartenstein and Keevallik, editors, Tallinin, Estonia, September. Springer-Verlag
-
Timothy J. Callahan and John Wawrzynek. Instruction level parallelism for reconfigurable computing. In Hartenstein and Keevallik, editors, International Conference on Field Programmable Logic and Applications (FPL), volume 1482 of Lecture Notes in Computer Science, Tallinin, Estonia, September 1998. Springer-Verlag.
-
(1998)
International Conference on Field Programmable Logic and Applications (FPL), Volume 1482 of Lecture Notes in Computer Science
, vol.1482
-
-
Callahan, T.J.1
Wawrzynek, J.2
-
25
-
-
0033358960
-
Predicated static single assignment
-
October
-
Lori Carter, Beth Simon, Brad Calder, Larry Carter, and Jeanne Ferrante. Predicated static single assignment. In International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.
-
(1999)
International Conference on Parallel Architectures and Compilation Techniques (PACT)
-
-
Carter, L.1
Simon, B.2
Calder, B.3
Carter, L.4
Ferrante, J.5
-
26
-
-
0034507852
-
Path analysis and renaming for predicated instruction scheduling
-
Lori Carter, Beth Simon, Brad Calder, Larry Carter, and Jeanne Ferrante. Path analysis and renaming for predicated instruction scheduling. International Journal of Parallel Programming, special issue, 28(6), 2000.
-
(2000)
International Journal of Parallel Programming, Special Issue
, vol.28
, Issue.6
-
-
Carter, L.1
Simon, B.2
Calder, B.3
Carter, L.4
Ferrante, J.5
-
27
-
-
0010548484
-
Stream computations organized for reconfigurable execution (SCORE): Introduction and tutorial
-
Lecture Notes in Computer Science. Springer Verlag
-
Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, André DeHon, and John Wawrzynek. Stream computations organized for reconfigurable execution (SCORE): Introduction and tutorial. In International Conference on Field Programmable Logic and Applications (FPL), Lecture Notes in Computer Science. Springer Verlag, 2000.
-
(2000)
International Conference on Field Programmable Logic and Applications (FPL)
-
-
Caspi, E.1
Chu, M.2
Huang, R.3
Yeh, J.4
Markovskiy, Y.5
DeHon, A.6
Wawrzynek, J.7
-
28
-
-
0036054368
-
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
-
New York, June 10-14. ACM Press
-
Tiberiu Chelcea and Steven M. Nowick. Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. In DAC, pages 405-410, New York, June 10-14 2002. ACM Press.
-
(2002)
DAC
, pp. 405-410
-
-
Chelcea, T.1
Nowick, S.M.2
-
29
-
-
84957700098
-
Effective representation of aliases and indirect memory operations in SSA form
-
April
-
Fred Chow, Raymond Lo, Shin-Ming Liu, Sun Chan, and Mark Streich. Effective representation of aliases and indirect memory operations in SSA form. In International Conference on Compiler Construction (CC), pages 253-257, April 1996.
-
(1996)
International Conference on Compiler Construction (CC)
, pp. 253-257
-
-
Chow, F.1
Lo, R.2
Liu, S.-M.3
Chan, S.4
Streich, M.5
-
30
-
-
0002927078
-
High speed: Not the only way to exploit the intrinsic computational power of silicon
-
San Francisco, CA. IEEE Catalog Number: 99CH36278
-
T.A.C.M. Claasen. High speed: not the only way to exploit the intrinsic computational power of silicon. In IEEE International Solid-State Circuits Conference, pages 22-25, San Francisco, CA, 1999. IEEE Catalog Number: 99CH36278.
-
(1999)
IEEE International Solid-State Circuits Conference
, pp. 22-25
-
-
Claasen, T.A.C.M.1
-
31
-
-
35048830785
-
An efficient static analysis algorithm to detect redundant memory operations
-
Berlin, Germany, June
-
Keith D. Cooper and Li Xu. An efficient static analysis algorithm to detect redundant memory operations. In Workshop on Memory Systems Performance (MSP '02), Berlin, Germany, June 2002.
-
(2002)
Workshop on Memory Systems Performance (MSP '02)
-
-
Cooper, K.D.1
Xu, L.2
-
35
-
-
0026243790
-
Efficiently computing static single assignment form and the control dependence graph
-
R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. ACM Transactions on Programming Languages and Systems (TOPLAS), 13(4):451-490, 1991.
-
(1991)
ACM Transactions on Programming Languages and Systems (TOPLAS)
, vol.13
, Issue.4
, pp. 451-490
-
-
Cytron, R.1
Ferrante, J.2
Rosen, B.3
Wegman, M.4
Zadeck, K.5
-
38
-
-
6444245678
-
A design environment for high throughput, low power dedicated signal processing systems
-
March
-
W. R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, M. J. Ammer, E. Yeo, S. Augsburger, B. Nikolic, and R. W. Brodersen, A design environment for high throughput, low power dedicated signal processing systems. IEEE Journal of Solid-State Circuits, 37(3):420-431, March 2002.
-
(2002)
IEEE Journal of Solid-state Circuits
, vol.37
, Issue.3
, pp. 420-431
-
-
Davis, W.R.1
Zhang, N.2
Camera, K.3
Markovic, D.4
Smilkstein, T.5
Ammer, M.J.6
Yeo, E.7
Augsburger, S.8
Nikolic, B.9
Brodersen, R.W.10
-
40
-
-
84937641774
-
First version of a data flow procedure language
-
Springer-Verlag: Berlin, New York
-
Jack B. Dennis. First version of a data flow procedure language. In Lecture Notes in Computer Science 19: Programming Symposium, pages 362-376. Springer-Verlag: Berlin, New York, 1974.
-
(1974)
Lecture Notes in Computer Science 19: Programming Symposium
, pp. 362-376
-
-
Dennis, J.B.1
-
41
-
-
0010584547
-
Bridging the gap between compilation and synthesis in the DEFACTO system
-
Pedro Diniz, Mary Hall, Joonseok Park, Byoungro So, and Heidi Ziegler. Bridging the gap between compilation and synthesis in the DEFACTO system. In Workshop on Languages and Compilers for Parallel Computing (LCPC), 2001.
-
(2001)
Workshop on Languages and Compilers for Parallel Computing (LCPC)
-
-
Diniz, P.1
Hall, M.2
Park, J.3
So, B.4
Ziegler, H.5
-
42
-
-
0031382165
-
Mapping applications to the RaPiD configurable architecture
-
Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, and Stefan G. Berg. Mapping applications to the RaPiD configurable architecture. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 1997.
-
(1997)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
-
-
Ebeling, C.1
Cronquist, D.C.2
Franklin, P.3
Secosky, J.4
Berg, S.G.5
-
43
-
-
0036173333
-
Balsa: An asynchronous hardware synthesis language
-
D. Edwards and A. Bardsley. Balsa: An asynchronous hardware synthesis language. The Computer J., 45(1):12-18, 2002.
-
(2002)
The Computer J.
, vol.45
, Issue.1
, pp. 12-18
-
-
Edwards, D.1
Bardsley, A.2
-
46
-
-
0013414135
-
An open graph visualization system and its applications to software engineering
-
Emden Gansner and Stephen North. An open graph visualization system and its applications to software engineering. Software Practice And Experience, 1(5), 1999. http://www.research.att.com/sw/tools/graphviz.
-
(1999)
Software Practice and Experience
, vol.1
, Issue.5
-
-
Gansner, E.1
North, S.2
-
49
-
-
0002392552
-
Hardware synthesis from C/C++
-
Munich, Germany, March
-
A. Ghosh, J. Kunkel, and S. Liao. Hardware synthesis from C/C++. In Design, Automation and Test in Europe (DATE), pages 384-387, Munich, Germany, March 1999.
-
(1999)
Design, Automation and Test in Europe (DATE)
, pp. 384-387
-
-
Ghosh, A.1
Kunkel, J.2
Liao, S.3
-
50
-
-
84947928895
-
Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
-
W. Moore and W. Luk, editors, Oxford, England, August, Springer
-
M. Gokhale and A. Marks. Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays. In W. Moore and W. Luk, editors, International Conference on Field Programmable Logic and Applications (FPL), pages 399-408, Oxford, England, August 1995, Springer.
-
(1995)
International Conference on Field Programmable Logic and Applications (FPL)
, pp. 399-408
-
-
Gokhale, M.1
Marks, A.2
-
51
-
-
84949813785
-
Stream-oriented FPGA computing in the Streams-C high level language
-
M. Gokhale, J. Stone, J. Arnold, and M. Kalinowski. Stream-oriented FPGA computing in the Streams-C high level language. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 49-56, 2000.
-
(2000)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
, pp. 49-56
-
-
Gokhale, M.1
Stone, J.2
Arnold, J.3
Kalinowski, M.4
-
53
-
-
0032674517
-
PipeRench: A coprocessor for streaming multimedia acceleration
-
Atlanta, GA
-
Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer. PipeRench: a coprocessor for streaming multimedia acceleration. In International Symposium on Computer Architecture (ISCA), pages 28-39, Atlanta, GA, 1999.
-
(1999)
International Symposium on Computer Architecture (ISCA)
, pp. 28-39
-
-
Goldstein, S.C.1
Schmit, H.2
Moe, M.3
Budiu, M.4
Cadambi, S.5
Taylor, R.R.6
Laufer, R.7
-
55
-
-
0036048303
-
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
-
ACM Press
-
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau, Timothy Kam, Michael Kishinevsky, and Shai Rotem. Coordinated transformations for high-level synthesis of high performance microprocessor blocks. In Design Automation Conference (DAC), pages 898-903. ACM Press, 2002.
-
(2002)
Design Automation Conference (DAC)
, pp. 898-903
-
-
Gupta, S.1
Savoiu, N.2
Dutt, N.3
Gupta, R.4
Nicolau, A.5
Kam, T.6
Kishinevsky, M.7
Rotem, S.8
-
56
-
-
0034854479
-
Speculation techniques for high level synthesis of control intensive designs
-
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, and Alexandra Nicolau. Speculation techniques for high level synthesis of control intensive designs. In Design Automation Conference (DAC), pages 269-272, 2001.
-
(2001)
Design Automation Conference (DAC)
, pp. 269-272
-
-
Gupta, S.1
Savoiu, N.2
Kim, S.3
Dutt, N.D.4
Gupta, R.K.5
Nicolau, A.6
-
57
-
-
33646922057
-
The future of wires
-
April
-
R. Ho, K. Mai, and M. Horowitz. The future of wires. IEEE Journal, 89(4):490-504, April 2001.
-
(2001)
IEEE Journal
, vol.89
, Issue.4
, pp. 490-504
-
-
Ho, R.1
Mai, K.2
Horowitz, M.3
-
58
-
-
0003843704
-
Communicating sequential processes
-
C. A. A. Hoare and C. B. Jones (Ed.), Prentice Hall
-
Hoare. Communicating sequential processes. In C. A. A. Hoare and C. B. Jones (Ed.), Essays in Computing Science, Prentice Hall. 1989.
-
(1989)
Essays in Computing Science
-
-
Hoare1
-
60
-
-
12344316973
-
Programming a Xilinx FPGA in "C"
-
Doug Johnson. Programming a Xilinx FPGA in "C". Xcell Quarterly Journal, 34, 1999.
-
(1999)
Xcell Quarterly Journal
, vol.34
-
-
Johnson, D.1
-
61
-
-
12344333540
-
Hardware synthesis with bach system
-
Orlando
-
Andrew Kay, Toshio Nomura, Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, and Takashi Kambe. Hardware synthesis with Bach system. In IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, 1999.
-
(1999)
IEEE International Symposium on Circuits and Systems (ISCAS)
-
-
Kay, A.1
Nomura, T.2
Yamada, A.3
Nishida, K.4
Sakurai, R.5
Kambe, T.6
-
63
-
-
0019923189
-
Why systolic architectures?
-
H. T. Kung. Why systolic architectures? IEEE Computer, 15(1):37-46, 1982.
-
(1982)
IEEE Computer
, vol.15
, Issue.1
, pp. 37-46
-
-
Kung, H.T.1
-
66
-
-
0032681044
-
ECL: A specification environment for system-level design
-
New Orleans, LA, June
-
Luciano Lavagno and Ellen Sentovich. ECL: A specification environment for system-level design. In Design Automation Conference (DAC), pages 511-516, New Orleans, LA, June 1999.
-
(1999)
Design Automation Conference (DAC)
, pp. 511-516
-
-
Lavagno, L.1
Sentovich, E.2
-
68
-
-
0031599788
-
Space-time scheduling of instruction-level parallelism on a Raw machine
-
Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe. Space-time scheduling of instruction-level parallelism on a Raw machine. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 46-57, 1998.
-
(1998)
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
, pp. 46-57
-
-
Lee, W.1
Barua, R.2
Frank, M.3
Srikrishna, D.4
Babb, J.5
Sarkar, V.6
Amarasinghe, S.7
-
69
-
-
0033720597
-
Hardware-software co-design of embedded reconfigurable architectures
-
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph Harr, Uday Kurkure, and Jon Stockwood. Hardware-software co-design of embedded reconfigurable architectures. In Design Automation Conference (DAC), 2000.
-
(2000)
Design Automation Conference (DAC)
-
-
Li, Y.1
Callahan, T.2
Darnell, E.3
Harr, R.4
Kurkure, U.5
Stockwood, J.6
-
70
-
-
0030704440
-
An efficient implementation of reactivity for modeling hardware in the Scenic design environment
-
Stan Liao, Steven W. K. Tjiang, and Rajesh Gupta. An efficient implementation of reactivity for modeling hardware in the Scenic design environment. In Design Automation Conference (DAC), pages 70-75, 1997.
-
(1997)
Design Automation Conference (DAC)
, pp. 70-75
-
-
Liao, S.1
Tjiang, S.W.K.2
Gupta, R.3
-
71
-
-
0038111456
-
-
Master's thesis, California Institute of Technology, Computer Science Department. CS-TR-95-21
-
Andrew Matthew Lines. Pipelined asynchronous circuits. Master's thesis, California Institute of Technology, Computer Science Department, 1995. CS-TR-95-21.
-
(1995)
Pipelined Asynchronous Circuits
-
-
Lines, A.M.1
-
72
-
-
0347507558
-
Register promotion by sparse partial redundancy elimination of loads and stores
-
ACM Press
-
Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26-37. ACM Press, 1998.
-
(1998)
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
, pp. 26-37
-
-
Lo, R.1
Chow, F.2
Kennedy, R.3
Liu, S.-M.4
Tu, P.5
-
74
-
-
0029202471
-
A comparison of full and partial predicated execution support for ILP processors
-
Santa Margherita Ligure, Italy, May. ACM
-
Scott A. Mahlke, Richard E. Hauk, James E. McCormick, David I. August, and Wen mei W. Hwu. A comparison of full and partial predicated execution support for ILP processors. In International Symposium on Computer Architecture (ISCA), pages 138-149, Santa Margherita Ligure, Italy, May 1995. ACM.
-
(1995)
International Symposium on Computer Architecture (ISCA)
, pp. 138-149
-
-
Mahlke, S.A.1
Hauk, R.E.2
McCormick, J.E.3
August, D.I.4
Hwu, W.M.W.5
-
75
-
-
0026980852
-
Effective compiler support for predicated execution using the hyperblock
-
Dec
-
Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, and Roger A. Bringmann. Effective compiler support for predicated execution using the hyperblock. In International Symposium on Computer Architecture (ISCA), pages 45-54, Dec 1992.
-
(1992)
International Symposium on Computer Architecture (ISCA)
, pp. 45-54
-
-
Mahlke, S.A.1
Lin, D.C.2
Chen, W.Y.3
Hank, R.E.4
Bringmann, R.A.5
-
76
-
-
0033688597
-
Smart memories: A modular reconfigurable architecture
-
June
-
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, and Mark Horowitz. Smart memories: A modular reconfigurable architecture. In International Symposium on Computer Architecture (ISCA), June 2000.
-
(2000)
International Symposium on Computer Architecture (ISCA)
-
-
Mai, K.1
Paaske, T.2
Jayasena, N.3
Ho, R.4
Dally, W.J.5
Horowitz, M.6
-
77
-
-
0002927123
-
Programming in VLSI: From communicating processes to delay-insensitive circuits
-
C. A. R. Hoare, editor, UT Year of Programming Series. Addison-Wesley
-
A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, pages 1-64. Addison-Wesley, 1990.
-
(1990)
Developments in Concurrency and Communication
, pp. 1-64
-
-
Martin, A.J.1
-
78
-
-
77957951589
-
The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller
-
May
-
Alain J. Martin, Mika Nystrm, Karl Papadantonakis, Paul I. Penzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, and Ahmet Tura. The Lutonium: A sub-nanojoule asynchronous 8051 microcontroller. In International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), May 2003.
-
(2003)
International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC)
-
-
Martin, A.J.1
Nystrm, M.2
Papadantonakis, K.3
Penzes, P.I.4
Prakash, P.5
Wong, C.G.6
Chang, J.7
Ko, K.S.8
Lee, B.9
Ou, E.10
Pugh, J.11
Talvala, E.-V.12
Tong, J.T.13
Tura, A.14
-
80
-
-
84976683916
-
-
OCCAM. May
-
D. May. OCCAM. SIGPLAN Notices, 18(4):69-79, May 1983.
-
(1983)
SIGPLAN Notices
, vol.18
, Issue.4
, pp. 69-79
-
-
May, D.1
-
83
-
-
84963624364
-
The program dependence web: A representation supporting control-, data-, and demand-driven interpretation of imperative languages
-
Karl J. Ottenstein, Robert A. Ballance, and Arthur B. Maccabe. The program dependence web: a representation supporting control-, data-, and demand-driven interpretation of imperative languages. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 257-271, 1990.
-
(1990)
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
, pp. 257-271
-
-
Ottenstein, K.J.1
Ballance, R.A.2
Maccabe, A.B.3
-
84
-
-
84984058313
-
Dependence flow graphs: An algebraic approach to program dependencies
-
Keshav Pingali, Micah Beck, Richard Johnson, Mayan Moudgill, and Paul Stodghill. Dependence flow graphs: An algebraic approach to program dependencies. In ACM Symposium on Principles of Programming Languages (POPL), volume 18, 1991.
-
(1991)
ACM Symposium on Principles of Programming Languages (POPL)
, vol.18
-
-
Pingali, K.1
Beck, M.2
Johnson, R.3
Moudgill, M.4
Stodghill, P.5
-
86
-
-
0035188663
-
Arithmetic logic circuits using self-timed bit level dataflow and early evaluation
-
Austin, TX, September 23-26
-
Robert B. Reese, Mitch A. Thornton, and Cherrice Traver. Arithmetic logic circuits using self-timed bit level dataflow and early evaluation. In International Conference on Computer Design (ICCD), page 18, Austin, TX, September 23-26 2001.
-
(2001)
International Conference on Computer Design (ICCD)
, pp. 18
-
-
Reese, R.B.1
Thornton, M.A.2
Traver, C.3
-
87
-
-
0035242871
-
An automated process for compiling dataflow graphs into hardware
-
February
-
R. Rinker, M. Carter, A. Patel, M. Chawathe, C. Ross, J. Hammes, W. Najjar, and A.P.W. Böhm. An automated process for compiling dataflow graphs into hardware. IEEE Transactions on VLSI, 9(1), February 2001.
-
(2001)
IEEE Transactions on VLSI
, vol.9
, Issue.1
-
-
Rinker, R.1
Carter, M.2
Patel, A.3
Chawathe, M.4
Ross, C.5
Hammes, J.6
Najjar, W.7
Böhm, A.P.W.8
-
88
-
-
0032312385
-
A bandwidth-efficient architecture for media processing
-
December
-
Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, and John D. Owens. A bandwidth-efficient architecture for media processing. In IEEE/ACM International Symposium on Microarchitecture (MICRO), December 1998.
-
(1998)
IEEE/ACM International Symposium on Microarchitecture (MICRO)
-
-
Rixner, S.1
Dally, W.J.2
Kapasi, U.J.3
Khailany, B.4
López-Lagunas, A.5
Mattson, P.R.6
Owens, J.D.7
-
91
-
-
0031619503
-
A programming environment for the design of complex high speed ASICs
-
San Francisco, June
-
P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, and I. Bolsens. A programming environment for the design of complex high speed ASICs. In Design Automation Conference (DAC), pages 315-320, San Francisco, June 1998.
-
(1998)
Design Automation Conference (DAC)
, pp. 315-320
-
-
Schaumont, P.1
Vernalde, S.2
Rijnders, L.3
Engels, M.4
Bolsens, I.5
-
93
-
-
0031354358
-
Compilers for instruction-level parallelism
-
This was a report from a cross-industry task force on ILP
-
M. Schlansker, T.M. Conte, J. Dehnen, K. Ebcioglu, J.Z. Fang, and C.L. Thompson. Compilers for instruction-level parallelism. IEEE Computer, 30(12):63-69, 1997. This was a report from a cross-industry task force on ILP.
-
(1997)
IEEE Computer
, vol.30
, Issue.12
, pp. 63-69
-
-
Schlansker, M.1
Conte, T.M.2
Dehnen, J.3
Ebcioglu, K.4
Fang, J.Z.5
Thompson, C.L.6
-
94
-
-
12344291385
-
PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators
-
R. Schreiber, S. Aditya (Gupta), B.R. Rau, S. Mahlke, V. Kathail, B. Ra. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.
-
(2001)
Journal of VLSI Signal Processing
-
-
Schreiber, R.1
Aditya, S.2
Rau, B.R.3
Mahlke, S.4
Kathail, V.5
Rau, B.Ra.6
Cronquist, D.7
Sivaraman, M.8
-
95
-
-
0035704608
-
Synthesis of hardware models in C with pointers and complex data structures
-
Luc Séméria, Koichi Sato, and Giovanni De Micheli. Synthesis of hardware models in C with pointers and complex data structures. IEEE Transactions on VLSI, 2001.
-
(2001)
IEEE Transactions on VLSI
-
-
Séméria, L.1
Sato, K.2
De Micheli, G.3
-
97
-
-
77953098085
-
Implementing C algorithms in reconfigurable hardware using C2Verilog
-
Kenneth L. Pocek and Jeffrey Arnold, editors, Los Alamitos, CA, April. IEEE Computer Society Press
-
Donald Soderman and Yuri Panchul. Implementing C algorithms in reconfigurable hardware using C2Verilog. In Kenneth L. Pocek and Jeffrey Arnold, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 339-342, Los Alamitos, CA, April 1998. IEEE Computer Society Press.
-
(1998)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
, pp. 339-342
-
-
Soderman, D.1
Panchul, Y.2
-
99
-
-
0024683698
-
Micropipelines: Turing award lecture
-
June
-
Ivan Sutherland. Micropipelines: Turing award lecture. Communications of the ACM, 32 (6):720-738, June 1989.
-
(1989)
Communications of the ACM
, vol.32
, Issue.6
, pp. 720-738
-
-
Sutherland, I.1
-
100
-
-
12344292557
-
WaveScalar
-
Washington University at Seattle, Computer Science Department, January
-
Steven Swanson, Ken Michelson, and Mark Oskin. WaveScalar. Technical Report 2003-01-01, Washington University at Seattle, Computer Science Department, January 2003.
-
(2003)
Technical Report 2003-01-01
-
-
Swanson, S.1
Michelson, K.2
Oskin, M.3
-
101
-
-
12344264897
-
Implementation and evaluation of the compiler for WASMII, a virtual hardware system
-
A. Takayama, Y. Shibata, K. Iwai, H. Miyazaki, K. Higure, and X.-P. Ling. Implementation and evaluation of the compiler for WASMII, a virtual hardware system. In International Workshop on Parallel Processing, pages 346-351, 1999.
-
(1999)
International Workshop on Parallel Processing
, pp. 346-351
-
-
Takayama, A.1
Shibata, Y.2
Iwai, K.3
Miyazaki, H.4
Higure, K.5
Ling, X.-P.6
-
102
-
-
2942679232
-
Static tokens: Using dataflow to automate oncurrent pipeline synthesis
-
Heraklion, Crete, Greece, April
-
John Teifel and Rajit Manohar. Static tokens: Using dataflow to automate oncurrent pipeline synthesis. In International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 17-27, Heraklion, Crete, Greece, April 2004.
-
(2004)
International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC)
, pp. 17-27
-
-
Teifel, J.1
Manohar, R.2
-
104
-
-
12344303266
-
Implications of technology scaling on leakage reduction techniques
-
San Diego, CA, June
-
Y-F. Tsai, D. Duarte, N. Vijaykrishnan, and M.J. Irwin. Implications of technology scaling on leakage reduction techniques. In Design Automation Conference (DAC), San Diego, CA, June 2004.
-
(2004)
Design Automation Conference (DAC)
-
-
Tsai, Y.-F.1
Duarte, D.2
Vijaykrishnan, N.3
Irwin, M.J.4
-
107
-
-
0022964131
-
Dataflow machine architecture
-
Arthur H. Veen. Dataflow machine architecture. ACM Computing Surveys, 18 (4):365-396, 1986.
-
(1986)
ACM Computing Surveys
, vol.18
, Issue.4
, pp. 365-396
-
-
Veen, A.H.1
-
108
-
-
12344330497
-
C to asynchronous dataflow circuits: An end-to-end toolflow
-
Temecula, CA, June
-
Girish Venkataramani, Mihai Budiu, and Seth Copen Goldstein. C to asynchronous dataflow circuits: An end-to-end toolflow. In International Workshop on Logic Syntheiss, Temecula, CA, June 2004.
-
(2004)
International Workshop on Logic Syntheiss
-
-
Venkataramani, G.1
Budiu, M.2
Goldstein, S.C.3
-
109
-
-
0005702886
-
First draft of a report on the EDVAC
-
Contract No. W-670-ORD-492, Moore School of Electrical Engineering, University of Pennsylvania, Philadelphia. Reprinted (in part) in Randell, Brian. 1982, Springer-Verlag, Berlin Heidelberg, June
-
John von Neumann. First draft of a report on the EDVAC. Contract No. W-670-ORD-492, Moore School of Electrical Engineering, University of Pennsylvania, Philadelphia. Reprinted (in part) in Randell, Brian. 1982. Origins of Digital Computers: Selected Papers, Springer-Verlag, Berlin Heidelberg, June 1945.
-
(1945)
Origins of Digital Computers: Selected Papers
-
-
Von Neumann, J.1
-
110
-
-
0034428798
-
C-based SoC design flow and EDA tools: An ASIC and system vendor perspective
-
December
-
Kazutoshi Wakabayashi and Takumi Okamoto. C-based SoC design flow and EDA tools: An ASIC and system vendor perspective. IEEE Transactions on Computer-Aided Design, 19(12): 1507-1522, December 2000.
-
(2000)
IEEE Transactions on Computer-aided Design
, vol.19
, Issue.12
, pp. 1507-1522
-
-
Wakabayashi, K.1
Okamoto, T.2
-
111
-
-
84957917534
-
PRISM-II compiler and architecture
-
Napa Valley, CA, Apr
-
M. Wazlowski, L. Agarwal, T. Lee, A. Smith, E. Lam, P. Athanas, H. Silverman, and S. Ghosh. PRISM-II compiler and architecture. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 9-16, Napa Valley, CA, Apr 1993.
-
(1993)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
, pp. 9-16
-
-
Wazlowski, M.1
Agarwal, L.2
Lee, T.3
Smith, A.4
Lam, E.5
Athanas, P.6
Silverman, H.7
Ghosh, S.8
-
112
-
-
84976692695
-
SUIF: An infrastructure for research on parallelizing and optimizing compilers
-
December
-
Robert P. Wilson, Robert S. French, Christopher S. Wilson, Saman P. Amarasinghe, Jennifer M. Anderson, Steve W. K. Tjiang, Shih-Wei Liao, Chau-Wen Tseng, Mary W. Hall, Monica S. Lam, and John L. Hennessy. SUIF: An infrastructure for research on parallelizing and optimizing compilers. In ACM SIGPLAN Notices, volume 29, pages 31-37, December 1994.
-
(1994)
ACM SIGPLAN Notices
, vol.29
, pp. 31-37
-
-
Wilson, R.P.1
French, R.S.2
Wilson, C.S.3
Amarasinghe, S.P.4
Anderson, J.M.5
Tjiang, S.W.K.6
Liao, S.-W.7
Tseng, C.-W.8
Hall, M.W.9
Lam, M.S.10
Hennessy, J.L.11
-
113
-
-
0032099295
-
Hardware compilation: Translating programs into circuits
-
June
-
Niklaus Wirth. Hardware compilation: Translating programs into circuits. IEEE Computer, 31 (6):25-31, June 1998.
-
(1998)
IEEE Computer
, vol.31
, Issue.6
, pp. 25-31
-
-
Wirth, N.1
-
114
-
-
0029545190
-
A dynamic instruction set computer
-
P. Athanas and K. L. Pocek, editors, Napa, CA, April
-
M. J. Wirthlin and B. L. Hutchings. A dynamic instruction set computer. In P. Athanas and K. L. Pocek, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 99-107, Napa, CA, April 1995.
-
(1995)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
, pp. 99-107
-
-
Wirthlin, M.J.1
Hutchings, B.L.2
-
115
-
-
0030399910
-
OneChip: An FPGA processor with reconfigurable logic
-
J. Arnold and K. L. Pocek, editors, Napa, CA, April
-
R. D. Wittig and P. Chow. OneChip: An FPGA processor with reconfigurable logic. In J. Arnold and K. L. Pocek, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 126-135, Napa, CA, April 1996.
-
(1996)
IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
, pp. 126-135
-
-
Wittig, R.D.1
Chow, P.2
-
116
-
-
0033703884
-
CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable unit
-
ACM Computer Architecture News. ACM Press
-
Alex Zhi Ye, Andreas Moshovos, Scott Hauck, and Prithviraj Banerjee. CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable unit. In International Symposium on Computer Architecture (ISCA), ACM Computer Architecture News. ACM Press, 2000.
-
(2000)
International Symposium on Computer Architecture (ISCA)
-
-
Ye, A.Z.1
Moshovos, A.2
Hauck, S.3
Banerjee, P.4
|