Diagnosing crosstalk faults in sequential circuits using fault simulation

IEICE Transactions on Information and Systems

Volumn E85-D, Issue 10, 2002, Pages 1515-1525

  Takahashi, Hiroshi ^a   Phadoongsidhi, Marong ^b   Higami, Yoshinobu ^a   Saluja, Kewal K ^b   Takamatsu, Yuzo ^a  

^a EHIME UNIVERSITY   (Japan)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Crosstalk fault; Diagnosis; Fault simulation; Sequential circuits

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

CROSSTALK FAULTS;

SEQUENTIAL CIRCUITS;

EID: 12244260753     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (9)

1. W.Y. Chen, S.K. Gupta, and M.A. Breuer, "Analytic method for crosstalk delay and pulse analysis under non-ideal inputs," Proc. Int. Test Conf., pp.809-818, 1997.
2. W.Y. Chen, S.K. Gupta, and M.A. Breuer, "Test generation in VLSI circuits for crosstalk noise," Proc. Int. Test Conf., pp.641-650, 1998.
3. W.Y. Chen, S.K. Gupta, and M.A. Breuer, "Test generation for crosstalk-induced delay in integrated circuits," Proc. Int. Test Conf., pp.191-200, 1999.
4. W.Y. Chen, S.K. Gupta, and M.A. Breuer, "Test generation for crosstalk-induced delay faults: Framework and computational results," Proc. 9th Asian Test Symposium, pp.305-310, 2000.
5. N. Itazaki, Y. Idomoto, and K. Kinoshita, "A fault simulator method for crosstalk faults in synchronous sequential circuits," Proc. 26th Fault-Tolerant Computing Symp., pp.38-43, 1996.
6. K.J. Keller, H. Takahashi, K.K. Saluja, and Y. Takamatsu. "On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits." Proc. Int. Test Conf., pp.568-577, 2001.
7. T.P. Kelsey, K.K. Saluja, and S.Y. Lee, "An efficient algorithm for sequential circuit test generations," IEEE Trans. Comput., vol.42, no.11, pp.1361-1371, 1993.
8. A. Krstic, J.-J. Liou, Y.-M. Jiang, and K.-T. Cheng, "Delay testing considering crosstalk-induced effects," Proc. Int. Test Conf., pp.558-567, 2001.
9. T. Niermann and J.H. Patel, "Hitec: A test generation package for sequential circuits," Proc. European Design Automation Conf., pp.214-218, 1991.