Noise analysis in a 0.8 V forward body-bias CMOS op-amp design

Fluctuation and Noise Letters

Volumn 4, Issue 2, 2004, Pages

  Zhang, C ^a   Srivastava, A ^a   Ajmera, P K ^a  

^a LOUISIANA STATE UNIVERSITY   (United States)

Author keywords

CMOS op amp; Forward body bias; Low power amplifier; Noise

Indexed keywords

EID: 12144255797     PISSN: 02194775     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0219477504001975     Document Type: Article

References (8)

1. B. J. Blalock, P. E. Allen and G. A. Rincon-Mora, Designing 1-V op amps using standard digital CMOS technology, IEEE Trans. Circuits and System-II 45 (1998) 769-779.
2. T. Lehmann and M. Cassia, 1-V power supply CMOS cascade amplifier, IEEE J. of Solid-State Circuits 36 (2001) 1082-1086.
3. M. Marin, M. J. Deen, M. de Murcia, P. Llinares and J. Vildeuil, Effects of body biasing on the low frequency noise behavior of NMOSFETs from a 130-nm CMOS technology, Proc. of SPIE 5113 (2003) 56-65.
4. A. Srivastava and D. Govindarajan, A fast ALU design in CMOS for low voltage operation, J. VLSI Design 14 (4) (2002) 315-327.
5. C. Zhang, A. Srivastava and P. K. Ajmera, A 0.8 V ultra-low power CMOS operational amplifier design, Proc. 45th IEEE International Midwest Symposium on Circuits and Systems, I, (Tulsa, OK, Aug. 4-7, 2002) 9-12.
6. P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley (1993) 744-747.
7. M. J. Deen and O. Marinov, Effect of forward and reverse substrate biasing on low frequency noise in silicon PMOSFETs, IEEE Trans. Electron Devices 49 (3) (2002) 409-413.
8. P. Gray and R. Meyer, MOS operational amplifier design-a tutorial overview, IEEE J. of Solid-State Circuits SC-17 (1982) 969-982.