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Volumn , Issue 416 PART 1, 1998, Pages 427-432

An original design of MOSFET/IGBT gate circuit layout to suppress power/drive interaction

Author keywords

Common impedance; EMC; PEEC method; Power drive interaction

Indexed keywords


EID: 11744304959     PISSN: 03796566     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (3)

References (8)
  • 1
    • 0029746418 scopus 로고    scopus 로고
    • Switching Disturbance Due to Source Inductance for a Power MOSFET : Analysis and Solution
    • F. Merienne, J. Roudet, JL. Schanen, "Switching Disturbance Due to Source Inductance for a Power MOSFET : Analysis and Solution", PESC'96, 1996,pp. 1743-1747.
    • (1996) PESC'96 , pp. 1743-1747
    • Merienne, F.1    Roudet, J.2    Schanen, J.L.3
  • 4
    • 0026942779 scopus 로고
    • Three-dimensional Interconnected Analysis Using Partial Element Equivalent Circuits
    • November
    • H. Heeb, A.E. Ruehli, "Three-dimensional Interconnected Analysis Using Partial Element Equivalent Circuits", IEEE Trans. on Circuits & Systems-Fundamental Theory and Application, vol. 39, No. 11, pp. 974-982, November 1992.
    • (1992) IEEE Trans. on Circuits & Systems-Fundamental Theory and Application , vol.39 , Issue.11 , pp. 974-982
    • Heeb, H.1    Ruehli, A.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.