CMOS/BiCMOS mixed design using tabu search

Electronics Letters

Volumn 34, Issue 14, 1998, Pages 1395-1396

  Sait, S M ^a   Youssef, H ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; OPTIMIZATION;

TABU SEARCH METHOD;

INTEGRATED CIRCUIT LAYOUT;

EID: 11744275436     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980984     Document Type: Article

References (6)

1. SAIT, S.M., and YOUSSEF, H.: 'Iterative computer algorithms and their applications in engineering'. IEEE Computer Society Press, 1998 (to appear)
2. BABA-ALI, A.R., and BELLAOUAR, A : 'An optimization tool for mixed CMOS/BiCMOS standard cells circuits', Arabian J. Sci. Eng., 1994, 19, (4B), pp. 883-888
3. BRAND, D., and VISWESWARIAH, C.: 'Inaccuracies in power estimation during logic synthesis'. IEEE/ACM Int. Conf. Computer Aided Design, November 1996, pp. 388-395
4. YOUSSEF, H., SAIT, S.M., and AL-FARRAH, K.: 'Timing influenced force-directed floorplanning'. European Design Automation Conf. with Euro-VHDL, Euro-DAC'95, Brighton, September 1995, pp. 156-161
5. YEN, S., et al.: 'Efficient algorithms for extracting the K-most critical paths in timing analysis'. Proc. 26th Design Automation Conf., 1989, pp. 649-654
6. GLOVER, F., and LAGUNA, M.: 'Tabu search' in REEVES, C. (Ed.): 'Modern heuristic techniques for combinatorial problems' (McGraw-Hill Book Co., Europe, 1995)