Modular leading one detector for logarithmic encoder

Electronics Letters

Volumn 34, Issue 8, 1998, Pages 727-728

  Lee, P ^a   Sartori, A ^b  

^a UNIVERSITY OF KENT   (United Kingdom)

^b ITC IRST   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SIGNAL ENCODING;

MODULAR LEADING ONE DETECTOR;

DETECTOR CIRCUITS;

EID: 11644254141     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980563     Document Type: Article

References (6)

1. SWARTZLANDER, E.E., and ALEXOPOULOS, A.G.: 'The sign/logarithm number system', IEEE Trans. Comput., 1975, pp. 1238-1242
2. KINGSBURY, N.G., and RAYNER, P.J.W.: 'Digital filtering using logarithmic arithmetic', Electron. Lett., 1971, 7, (2), pp. 56-58
3. KUROKAWA, T., PAYNE, J., and LEE, S.: 'Error analysis of recursive digital filters implemented with logarithmic number systems', IEEE Trans. ASSP, 1980, ASSP-28, (6), pp. 706-715
4. HOEFFLINGER, B.: 'Efficient VLSI digital logarithmic codecs', Electron. Lett., 1991, 27, (13), pp. 1132-1134
5. OKLOBDZIJA, V.G.: 'Algorithmic design of a heirarchical and modulator leading zero detector circuit', Electron. Lett., 1993, 29, (3), pp. 283-284
6. LEHMAN, M., and BURLA, N.: 'Skip techniques for high speed carry propogation in binary arithmetic circuits', IRE Trans. Electron. Comput., 1961, pp. 691-698